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Magician Harry Houdini patented a "Diver's Suit" enabling the wearer to "quickly divest himself of the suit while being submerged and to safely escape and reach the surface of the water."
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| Number | Title | Issue Date |
| 4245331 | Memory pack A memory pack is provided having a random access memory connected between a positive power source terminal and a ground terminal, an addressing terminal coupled with the random access memory, and a data input/output terminal coupled with the random access... | 01/13/1981 |
| 4236207 | Memory initialization circuit An initialization circuit for a dynamic memory element in a data processing system. The dynamic memory element comprises plural storage modules and a refreshing cycle counter that addresses individual storage locations in said modules in sequence. Address... | 11/25/1980 |
| 4229804 | Numerical control unit having a cassette type memory A numerical control unit in which command data is inputted from a keyboard and stored in an internal memory and which controls a machine tool based on the stored command data. A cassette type memory is constructed to be detachably mounted on the numerical... | 10/21/1980 |
| 4153937 | Microprocessor system having high order capability A microprocessor system with high order capabilities is provided with the two non-volatile memories which are read-only-memories (ROMs) in the disclosed embodiment. A first ROM stores the microcode for controlling the operation of the microprocessor circu... | 05/08/1979 |
| 4051460 | Apparatus for accessing an information storage device having defective memory cells An information storage device comprising an information storage unit consisting of a plurality of memory blocks each consisting of a plurality of memory cells, and means for storing therein the address information uniquely corresponding to said memory blo... | 09/27/1977 |
| 4028678 | Memory patching circuit A read only memory (ROM) patching arrangement is disclosed which provides valid output information whenever ROM locations containing invalid information are addressed. The disclosed arrangement detects the receipt of each ROM address word representing a d... | 06/07/1977 |
| 4028679 | Memory patching circuit with increased capability A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever defective ROM word locations containing invalid information are addressed. The disclosed arrangement, which includes a decoder comprising a pluralit... | 06/07/1977 |
| 4028683 | Memory patching circuit with counter A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever ROM word locations containing invalid information are addressed. The disclosed arrangement uses a plurality of small capacity PROMs as a decoder to ... | 06/07/1977 |
| 4028684 | Memory patching circuit with repatching capability A ROM patching facility is disclosed which permits any ROM address location containing defective information to be patched. New and updated program information is supplied to the system upon the detection of each address word that is to be patched. The di... | 06/07/1977 |
| 4019175 | Program changeable sequence controller A programmable sequence controller is disclosed which includes a controller memory having at least one read-only memory unit for storing a sequence program comprising a series of instructions each including an operation code and address information. An op... | 04/19/1977 |
| 3974479 | Memory for use in a computer system in which memories have diverse retrieval characteristics A memory unit for use with a central processor unit in a data processing system. To retrieve data from the memory unit, the central processor unit energizes an appropriate one of several memory retrieval control signal conductors and memory address signal... | 08/10/1976 |
| 3934227 | Memory correction system Correct data stored in an overlay memory register is furnished to a processor, instead of incorrect data stored in a fixed memory register addressed by the processor, by providing a mapping memory that is addressed simultaneously with the addressing of th... | 01/20/1976 |
