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| Number | Title | Issue Date |
| 8127074 | Mechanism for a reader page for a ring buffer In one embodiment, a mechanism for a reader page for a ring buffer is disclosed. In one embodiment, a method for implementing a reader page for a ring buffer includes allocating, by a processing device, a block of storage separate from a ring buffer as a reader page... | 02/28/2012 |
| 8099546 | Mechanism for a lockless ring buffer in overwrite mode In one embodiment, a mechanism for a lockless ring buffer in overwrite mode is disclosed. In one embodiment, a method for implementing a lockless ring buffer in overwrite mode includes aligning memory addresses for each page of a ring buffer to form maskable bits in... | 01/17/2012 |
| 8095727 | Multi-reader, multi-writer lock-free ring buffer A method for accessing cells of a ring buffer by one or more writers, wherein the one or more writers are prevented from simultaneously accessing a cell of the ring buffer. In addition, a method for accessing cells of a ring buffer by one or more readers, wherein th... | 01/10/2012 |
| 7644227 | Circulating first-in-first-out buffer A circulating first-in-first-out (FIFO) buffer with a downstream input and output, an upstream input and output, a circulating staging and staging marker and output marker storage with the same storage capacity; a circulating primary, begin marker, and end marker st... | 01/05/2010 |
| RE40904 | Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one in accordance with whether t... | 09/01/2009 |
| 7568066 | Reset system for buffer and method thereof A reset system for a buffer and a method thereof are disclosed. The reset system of the present invention includes a resettable flag in the buffer and a control unit. The reset method is to set the resettable flag and reset buffer so tat each exchanged processing un... | 07/28/2009 |
| 7558910 | Detecting access to a memory location in a multithreaded environment Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support f... | 07/07/2009 |
| 7415580 | System for determining the position of an element in memory A system for determining a position of an element in memory comprising a memory queue with a plurality of separate entries and propagate and generate logic in communication with the memory queue such that the propagate and generate logic is operable to inspect each ... | 08/19/2008 |
| 7404058 | Method and apparatus for avoiding collisions during packet enqueue and dequeue A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or stat... | 07/22/2008 |
| 7392338 | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously pe... | 06/24/2008 |
| 7386656 | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a ... | 06/10/2008 |
| 7383377 | Method and apparatus for transferring data A pointer comparing unit determines whether a value of a writing pointer is identical to a value of a reading pointer. When it is determined that the value of the writing pointer is different from the value of the reading pointer, an inter-memory transfer unit reads... | 06/03/2008 |
| 7366842 | Creating permanent storage on the fly within existing buffers A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache wi... | 04/29/2008 |
| 7366831 | Lock-free bounded FIFO queue mechanism A system includes a processor and a size bounded first-in first-out (FIFO) memory that is connected to the processor and a display is connected to the processor. A managing process to run on the processor to manage the FIFO memory structure. The FIFO memory includes... | 04/29/2008 |
| 7362764 | Method and apparatus for verifying service level in a communications network One embodiment of the invention provides apparatus and a method for handling an incoming packet at a port in a network. The port belongs to one or more partitions, and at least one service level is associated with each of the partitions. When a packet is received at... | 04/22/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7350040 | Method and system for securing metadata to detect unauthorized access Generally described, embodiments of the present invention provide a system and method for protecting a computer from malicious attacks and buffer overrun (intentional or unintentional). In particular, embodiments of the present invention protect the contents of bloc... | 03/25/2008 |
| 7327749 | Combined buffering of infiniband virtual lanes and queue pairs A system and method for shared buffering of InfiniBand virtual lanes and queue pairs. Instead of allocating dedicated memory space (e.g., a set of FIFO queues), a shared memory dynamically accommodates traffic received on different virtual lanes and/or queue pairs o... | 02/05/2008 |
| 7302648 | Method and apparatus for resizing buffered windows Methods and apparatuses for resizing buffered windows. In one aspect of the invention, a method to resize a buffered window on a data processing system includes: determining an estimated size for a window which has a first pixel image of a first size buffered in a f... | 11/27/2007 |
| 7296029 | Environmentally responsive oscillating circular affinity index Various embodiments of a method, apparatus and article of manufacture to manage an index are provided. A circular index, having an index size, is provided. The circular index stores information to reference data in a sequential list. Accesses to the index and the li... | 11/13/2007 |
| 7295552 | Cluster switching architecture A network switch including at least one data port interface supporting a plurality of data ports, at least one stack link interface configured to transmit data between the network switch and other network switches, and a CPU interface configured to communicate with ... | 11/13/2007 |
| 7293020 | String search scheme in a distributed architecture Methods and apparatuses for searching network data for one or more predetermined strings are disclosed. A multi-stage search may be performed by different hardware components. In a first search stage, a first processor may perform a comparison of blocks of incoming ... | 11/06/2007 |
| 7293132 | Apparatus and method for efficient data storage using a FIFO memory A first-in, first-out (FIFO) memory apparatus, a device, and a method include a memory that can store a data packet. A length of the data packet and the data packet are stored in the memory and the length and the data packet are flushed from the memory when the data... | 11/06/2007 |
| 7293212 | Memory self-test via a ring bus in a data processing apparatus A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of t... | 11/06/2007 |
| 7290095 | Information processing apparatus and method therefor, and recording medium An information processing apparatus, in which binding of data common to processes is performed such that common data is registered, and in which if it is determined that common data is not yet been registered, a task is shifted to a sleeping state and then shifted t... | 10/30/2007 |
| 7289998 | Method to update a data structure disposed in an embedded device A method to update a data structure is disclosed. The method receives a write thread, and sets a data structure indicator to indicate that the data structure is unusable. The method creates (N) thread indicators, and assigns each of said (N) indicators to a differen... | 10/30/2007 |
| 7275135 | Hardware updated metadata for non-volatile mass storage cache An apparatus and method to de-allocate data in a cache memory is disclosed. Using a clock that has a predetermined number of periods, the invention provides a usage timeframe information to approximate the usage information. The de-allocation decisions can then be m... | 09/25/2007 |
| 7275137 | Handling of the transmit enable signal in a dynamic random access memory controller A method, an apparatus, and a computer program are provided for controlling a transmission enable (TX_ENA) signal. In Extreme Data Rate (XDR™) Dynamic Random Access Memories (DRAMs) or XDRAMS, there is a requirement that a TX_ENA signal remain logic high for a few... | 09/25/2007 |
| 7272678 | DSP bus monitoring apparatus and method A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external... | 09/18/2007 |
| 7269608 | Apparatus and methods for caching objects using main memory and persistent memory An object cache stores objects in a cyclic buffer to provide highly efficient creation of cache entries. The cache efficiently manages storage of a large number of small objects because the cache does not write objects into a file system as individual files, rather ... | 09/11/2007 |
| 7266650 | Method, apparatus, and computer program product for implementing enhanced circular queue using loop counts A method, apparatus, and computer program product are provided for implementing an enhanced circular queue using loop counts for command processing. A circular queue includes a plurality of entries for storing commands. As command entries are added to the queue at t... | 09/04/2007 |
| 7259314 | Waveform data processing apparatus In a waveform data processing apparatus, a transfer section reads out waveform data of multiple tracks stored in a first storage device in data units, and transfers the read waveform data to a second storage device having an access speed higher than an access speed ... | 08/21/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7230917 | Apparatus and technique for conveying per-channel flow control information to a forwarding engine of an intermediate network node A flow bit mechanism and technique conveys per-channel flow control information pertaining to the status of output buffers located on line cards to at least one performance routing engine (PRE) of an intermediate network node, such as an aggregation router. Each lin... | 06/12/2007 |
| 7231490 | Storage device control apparatus and control method for the storage device control apparatus A storage device control apparatus includes a mounting part and an internal connection part. The mounting part can removably mount channel control unit, each with a host interface controller formed therein for receiving data I/O requests, disk control units, each wi... | 06/12/2007 |
| 7181548 | Command queueing engine The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and de... | 02/20/2007 |
| 7177877 | Method and system for externalizing conditional logic for collecting multi-purpose objects A method and system for externalizing conditional logic for an integrated programming architecture provides a static tree structure traversed by a dynamic object collector. The tree structure includes a plurality of conditional nodes and a plurality of branches for ... | 02/13/2007 |
| 7174432 | Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple proces... | 02/06/2007 |
| 7167934 | Peripheral device data transfer protocol A client driver requests data packet transfers from a peripheral device through a protocol stack and a host controller. The protocol stack receives the data transfer request and allocates the request into the host controller schedule. The host controller schedule re... | 01/23/2007 |
| 7167639 | Digital video recorder using circular file management and method of operation There is disclosed a digital video recorder that uses a circular file management system to efficiently manage time-shifted viewing a live video broadcast television program. There is provided for use in the digital video recorder, an apparatus for performing time-sh... | 01/23/2007 |
