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| Number | Title | Issue Date |
| 8122190 | Method and system for reconfigurable memory-based permutation implementation Memory-based permutation methods and systems are provided for the permutation of data. The memory-based permutation methods and systems provide flexibility and reconfigurability while reducing size and increasing speed. They provide the ability to program a memory, ... | 02/21/2012 |
| 7996604 | Class queue for network data switch to identify data memory locations by arrival time A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based o... | 08/09/2011 |
| 7941595 | Methods and systems for a memory section A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a ... | 05/10/2011 |
| 7930472 | Method for accessing a first-in-first-out (FIFO) buffer and a FIFO controller therefor A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data buffered in the FIFO buffer is more than a threshold. Second, pop the data... | 04/19/2011 |
| 7783827 | Data processor having a memory controller with cache memory The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable... | 08/24/2010 |
| 7769753 | Method and system for retrieving a data pattern A data retrieval system includes a retrieval request block for generating a retrieval key including a current state number and a current character string including N characters latched from an input character string, and a state transition memory operating for retri... | 08/03/2010 |
| 7673095 | FIFO memory architecture and method for the management of the same A FIFO memory with a frequency f and a size of M n-bit words, to successively store n-bit words received serially at an input and give said words serially at an output in the order in which they are stored, comprises a basic memory with a frequency f/2, capable of s... | 03/02/2010 |
| 7606969 | Programmable logic devices An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD fur... | 10/20/2009 |
| 7440532 | Bit slip circuitry for serial data signals Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least... | 10/21/2008 |
| 7421559 | Apparatus and method for a synchronous multi-port memory A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also inc... | 09/02/2008 |
| 7409717 | Metamorphic computer virus detection The executions of computer viruses are analyzed to develop register signatures for the viruses. The register signatures specify the sets of outputs the viruses produce when executed with a given set of inputs. A virus detection system (VDS) (400) holds a data... | 08/05/2008 |
| 7392417 | Device for exchanging data signals between two clock domains A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the para... | 06/24/2008 |
| 7362751 | Variable length switch fabric Variable length switch fabric for switching variable length data packets between input and output transmission paths in a communication network. In one embodiment of the invention, apparatus is provided for switching variable length data packets between input and ou... | 04/22/2008 |
| 7350059 | Managing stack transfers in a register-based processor The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers that are configured to emulate a top portion of a stack and memory, which... | 03/25/2008 |
| 7346739 | First-in-first-out memory system and method for providing same First-in-first-out (FIFO) memory system and method for providing the same is described. In one example, a dual-port memory circuit includes first storage locations for defining a plurality of FIFOs, second storage locations for storing status information for each of... | 03/18/2008 |
| 7340582 | Fault processing for direct memory access address translation An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested... | 03/04/2008 |
| 7334063 | Method and device for register access according to identifier register A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the regist... | 02/19/2008 |
| 7334078 | Method and system for handling streaming information One aspect of the present invention leads to a method of handling streaming information. The method includes receiving the streaming information and analyzing the streaming information to locate one or more points of interest in the streaming information. An index o... | 02/19/2008 |
| 7334112 | Method and apparatus for managing access to out-of-frame registers Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack includ... | 02/19/2008 |
| 7327632 | Interface circuit An interface apparatus having a first and a second buffer storage unit, the first buffer storage unit being associated with a first domain and the second buffer storage unit being associated with a second domain, and the buffer storage units being connected to one a... | 02/05/2008 |
| 7321518 | Apparatus and methods for providing redundancy in integrated circuits An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and de... | 01/22/2008 |
| 7293148 | Method for reliably verifying a memory area of a microcontroller in a control unit and control unit having a protected microcontroller A method is provided for controlling a microcontroller in a control unit in a motor vehicle, having a processor core, at least one read-only memory area and at least one rewritable memory area, at least one control program which is intended to be processed by the pr... | 11/06/2007 |
| 7290124 | Data processor employing register banks with overflow protection to enhance interrupt processing and task switching The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception o... | 10/30/2007 |
| 7290176 | Method and system for generating stacked register dumps from backing-store memory In various embodiments of the present invention, debugging and program-behavior-analysis software can reconstruct register-based processor states for nested routine calls from the backing-store memory employed by a modern processor, and by processors of similar arch... | 10/30/2007 |
| 7287169 | Electronic device and timer therefor with tamper event stamp features and related methods An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the ... | 10/23/2007 |
| 7275147 | Method and apparatus for data alignment and parsing in SIMD computer architecture Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and... | 09/25/2007 |
| 7272702 | Method and apparatus for managing access to out-of-frame registers Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack includ... | 09/18/2007 |
| 7266650 | Method, apparatus, and computer program product for implementing enhanced circular queue using loop counts A method, apparatus, and computer program product are provided for implementing an enhanced circular queue using loop counts for command processing. A circular queue includes a plurality of entries for storing commands. As command entries are added to the queue at t... | 09/04/2007 |
| 7260015 | Memory device and method having multiple internal data buses and memory bank interleaving A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of int... | 08/21/2007 |
| 7254670 | System, method, and apparatus for realizing quicker access of an element in a data structure This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base address. A fractional shifter is also included and is configured to shif... | 08/07/2007 |
| 7254699 | Aligning load/store data using rotate, mask, zero/sign-extend and or operation The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is disclosed for loading unaligned data stored in several memory locations, incl... | 08/07/2007 |
| 7243252 | Synchronization circuit for transferring data using a bus of a different width A semiconductor device that transmits data in wide bus width regardless of the width of an external data bus connected thereto. On the device's data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a t... | 07/10/2007 |
| 7243165 | Parallel pattern detection engine A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern ha... | 07/10/2007 |
| 7231499 | Prioritization of real time / non-real time memory requests from bus compliant devices One or more methods and systems of prioritizing access of physical memory space to bus compliant devices in a computing device is presented. Prioritization is based on real time or non-real time device functionality. In one embodiment, the method of accessing physic... | 06/12/2007 |
| 7225373 | Data transfer validation system System and apparatus for data validation is described. An initialization controller includes an initialization state machine. The initialization state machine is configured to cause configuration data to be transferred from memory internal or external to the integra... | 05/29/2007 |
| 7219212 | Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/15/2007 |
| 7216345 | Method and apparatus for protectively operating a data/information processing device A privilege level re-mapping mechanism is provided to a processor to re-map privilege levels. The re-mapping mechanism is placed in between the control registers and the privilege checking circuitry, to enable the re-mapping to be dynamically performed in real time ... | 05/08/2007 |
| 7213170 | Opportunistic CPU functional testing with hardware compare One embodiment disclosed relates to a method of providing CPU functional testing. Operations are executed on multiple functional units of a same type in the CPU. The outputs of the multiple functional units are automatically compared. The results of the comparison a... | 05/01/2007 |
| 7209405 | Memory device and method having multiple internal data buses and memory bank interleaving A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of int... | 04/24/2007 |
| 7206923 | Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling A method and apparatus is provided to manage data in computer registers in a program, making more computer registers available to one or more programmers utilizing a name level instruction. The method and apparatus disclosed herein presents a way of reducing the ove... | 04/17/2007 |
