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| Number | Title | Issue Date |
| 8176241 | System and method for optimizing DRAM refreshes in a multi-channel memory controller In accordance with the teachings of the present invention, a system and method for optimizing DRAM refreshes in a multi-channel memory controller are provided. In a particular embodiment, the method includes receiving, at a router in a light modulation system, a sig... | 05/08/2012 |
| 8171211 | Method and system for minimizing impact of refresh operations on volatile memory performance A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly sch... | 05/01/2012 |
| 8166238 | Method, device, and system for preventing refresh starvation in shared memory bank A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refr... | 04/24/2012 |
| 8161232 | Periodically and empirically determined memory refresh intervals Embodiments include a system, a memory controller, an apparatus, a device, and a method. An embodiment provides a device that includes a memory that requires a periodic refresh and having a nominal refresh period, and a processor operably coupled with the memory. Th... | 04/17/2012 |
| 8122188 | Method of controlling refresh operation in multi-port DRAM and a memory system using the method A multi-port memory system includes a shared memory bank, and a refresh controller coupled to the shared memory bank, and configured to selectively apply refresh commands from multiple processors to the shared memory bank. ... | 02/21/2012 |
| 8122187 | Refreshing dynamic volatile memory A memory system, and process for refreshing the memory, is disclosed. The memory system includes memory, a temperature sensor configured to measure the temperature of the memory, and a memory controller configured to refresh the memory at a refresh rate, the refresh... | 02/21/2012 |
| 8112577 | Concurrently communicating refresh and read/write commands with a memory device Disclosed are, inter alia, methods, apparatus, computer-readable media, mechanisms, and means for communicating with a memory device, such as by a memory controller, a refresh command at least partially overlapping in time with a read and/or write command. The refre... | 02/07/2012 |
| 8082387 | Methods, systems, and devices for management of a memory system Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with the architecture of currently existing operating systems. One such memory ma... | 12/20/2011 |
| 8037237 | Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the... | 10/11/2011 |
| 8024513 | Method and system for implementing dynamic refresh protocols for DRAM based cache A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refresha... | 09/20/2011 |
| 7996603 | DRAM controller that forces a refresh after a failed refresh request A refresh controller transmits two refresh request signals of a first request signal which indicates a time at which a refresh operation of a DRAM may be performed and a second request signal which indicates a time at which a refresh operation of the DRAM must be pe... | 08/09/2011 |
| 7966447 | Systems and methods for determining refresh rate of memory based on RF activities Systems and methods for determining a refresh rate of volatile memory are provided. In this regard, a representative system, among others, includes a radio frequency (RF) device; a computing device that communicates with the RF device, the computing device including... | 06/21/2011 |
| 7953921 | Directed auto-refresh synchronization In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon ent... | 05/31/2011 |
| 7937525 | Method and apparatus for decoding a virtual machine control structure identification Embodiments of apparatuses, methods, and systems for decoding a virtual machine control structure identification are disclosed. In one embodiment, an apparatus includes a virtual machine control structure to decode a virtual machine control structure identification ... | 05/03/2011 |
| 7930471 | Method and system for minimizing impact of refresh operations on volatile memory performance A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly sch... | 04/19/2011 |
| 7917692 | Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs s... | 03/29/2011 |
| 7882302 | Method and system for implementing prioritized refresh of DRAM based cache A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment per... | 02/01/2011 |
| 7870330 | Controller for refreshing memories A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device maintains a counter for each memory block or sector. When a memory block or sector is erased or programmed, th... | 01/11/2011 |
| 7844773 | Refresh circuit and refresh method in semiconductor memory device A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operatio... | 11/30/2010 |
| 7757039 | DRAM selective self refresh In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associa... | 07/13/2010 |
| 7747815 | Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the... | 06/29/2010 |
| 7734866 | Memory with address-differentiated refresh rate to accommodate low-retention storage rows In a dynamic random access memory device, receiving refresh commands via a signaling interface and, in response to the refresh commands, refreshing a first row of storage cells at a first refresh rate and refreshing a second row of storage cells at a second, faster ... | 06/08/2010 |
| 7653780 | Semiconductor memory device and control method thereof A semiconductor memory device that does not delay read/write access due to a refresh and can be interface compatible with a high-speed SRAM such as a QDR SRAM, comprises a plurality of subarrays each having a plurality of dynamic memory cells; at least one cache mem... | 01/26/2010 |
| 7640391 | Integrated circuit random access memory capable of automatic internal refresh of memory array A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on cloc... | 12/29/2009 |
| 7640392 | Non-DRAM indicator and method of accessing data not stored in DRAM array Data not stored in the DRAM array of a SDRAM module, such as the output of a temperature sensor, are read from the SDRAM in a synchronous read cycle that is seamlessly interspersed with SDRAM read and write cycles directed to data in the DRAM array. Control informat... | 12/29/2009 |
| 7617356 | Refresh port for a dynamic memory A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh logic performs a refresh to a portion of the memory array specified, at... | 11/10/2009 |
| 7613873 | Deferring refreshes during calibrations in memory systems A memory system employs calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions and interferences, refreshes are def... | 11/03/2009 |
| 7603512 | Dynamic memory refresh controller, memory system including the same and method of controlling refresh of dynamic memory A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a master device. The scheduler reorders the requests from the master device... | 10/13/2009 |
| 7565479 | Memory with refresh cycle donation to accommodate low-retention-storage rows In a dynamic random access memory device, refreshing each normal-retention row of storage cells once per refresh interval, refreshing each low-retention row of storage cells more than once per refresh interval and refreshing each high-retention row of storage cells ... | 07/21/2009 |
| 7565480 | Dynamic memory supporting simultaneous refresh and data-access transactions Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and prechar... | 07/21/2009 |
| 7543106 | Apparatus and method for controlling refresh of semiconductor memory device according to positional information of memory chips A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices according to positional information of memory chips of the memory devices. The refresh c... | 06/02/2009 |
| 7526602 | Memory control system and memory control circuit A memory control system includes a first memory for accessing a CPU via an address bus and a data bus, an SDRAM for accessing a CPU via the address bus and the data bus, a SDRAM control circuit for outputting a refresh request to the DRAM and a selection unit for se... | 04/28/2009 |
| 7516270 | Memory controller and method for scrubbing memory without using explicit atomic operations A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit ... | 04/07/2009 |
| 7444577 | Memory device testing to support address-differentiated refresh rates A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of stor... | 10/28/2008 |
| 7436728 | Fast random access DRAM management method including a method of comparing the address and suspending and storing requests A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing... | 10/14/2008 |
| 7437500 | Configurable high-speed memory interface subsystem A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic rando... | 10/14/2008 |
| 7433996 | System and method for refreshing random access memory cells A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request ... | 10/07/2008 |
| 7423925 | Memory A memory capable of performing a refresh operation uncompetitively with an internal access operation also when an external access operation is non-cyclically performed is obtained. This memory comprises an external access detection portion detecting an external acce... | 09/09/2008 |
| 7392339 | Partial bank DRAM precharge A “partial PRECHARGE command” is used to precharge a fraction of the banks in a multi-bank DRAM. In a first implementation the command precharges one half of the banks. In a second implementation the command precharges one quarter of the banks. The power drawn b... | 06/24/2008 |
| 7379323 | Memory with a refresh portion for rewriting data This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies with respect to the plurality of memory cell blocks detected by the f... | 05/27/2008 |
