Quotables
"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8190814 | Memory access apparatus and display using the same A memory access apparatus and a display using the same are provided. The memory access apparatus includes a dynamic memory, a plurality of clients and a memory management unit. The dynamic memory is used to store a plurality of memory data. The clients access the dy... | 05/29/2012 |
| 8180957 | Memory control unit and memory control method An object of the invention is to provide a memory control unit and a memory control method capable of making the operation setting of SDRAM without intentionally stopping access to the SDRAM. A switch signal generation section (18) for generating a switch sig... | 05/15/2012 |
| 8176240 | Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of ... | 05/08/2012 |
| 8171210 | Semiconductor memory, operating method of semiconductor memory, and system Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the seco... | 05/01/2012 |
| 8166237 | Configurable allocation of thread queue resources in an FPGA A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random a... | 04/24/2012 |
| 8151042 | Method and system for providing identification tags in a memory system having indeterminate data response times A method and system for providing identification tags in a memory system having indeterminate data response times. An exemplary embodiment includes a memory controller in a memory system. The memory controller includes a mechanism for receiving data packets via an u... | 04/03/2012 |
| 8140743 | Semiconductor memory device and method for operating semiconductor memory device A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section, the memory array section and the int... | 03/20/2012 |
| 8122186 | Memory device, memory system and dual port memory device with self-copy function A memory device with a self-copy function includes a memory cell array having first and second banks, and a memory interface. The memory interface reads data from a memory area of the first bank corresponding to a source address contained in previously set self-copy... | 02/21/2012 |
| 8108596 | Memory controller address mapping scheme A data processing system is provided with a memory controller (130) converting memory addresses (170) into selecting signals (120) for a memory device (100). The mapping between memory addresses and selecting signals is provided by mappin... | 01/31/2012 |
| 8095725 | Device, system, and method of memory allocation Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each b... | 01/10/2012 |
| 8060692 | Memory controller using time-staggered lockstep sub-channels with buffered memory Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-... | 11/15/2011 |
| 8032695 | Multi-path accessible semiconductor memory device with prevention of pre-charge skip A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors accordi... | 10/04/2011 |
| 8024512 | Memory controller and data processing system A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high... | 09/20/2011 |
| 8006033 | Systems, methods, and apparatuses for in-band data mask bit transmission Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the ... | 08/23/2011 |
| 8006032 | Optimal solution to control data channels A dynamic random access memory (DRAM) controller may comprise two sub-controllers, each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to cont... | 08/23/2011 |
| 7996602 | Parallel memory device rank selection A translator of an apparatus in an example selects one or more ranks of parallel memory devices from a plurality of available ranks of parallel memory devices in a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered... | 08/09/2011 |
| 7996601 | Apparatus and method of partially accessing dynamic random access memory Provided are an apparatus and method for partially accessing a DRAM. The apparatus for partially accessing a DRAM includes a memory controller. The memory controller includes a first sub-controller which controls a first DRAM and a second sub-controller which contro... | 08/09/2011 |
| 7984234 | Memory control apparatus and memory control method A memory control apparatus and a memory control method are provided to enable an effective utilization of buffer memory in a system LSI by comprising buffer memory for temporarily storing data stored in memory, and comprising the processes of: receiving an instructi... | 07/19/2011 |
| 7966446 | Memory system and method having point-to-point link A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal fro... | 06/21/2011 |
| 7941594 | SDRAM sharing using a control surrogate A system and method for sharing a single synchronous dynamic random access memory (SDRAM) unit between two chips, each having an SDRAM controller. Each SDRAM controller is effectively divided into a control block and a data block. The first SDRAM controller drives o... | 05/10/2011 |
| 7930470 | System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller A memory system is provided that manages thermal conditions at a memory device level transparent to a memory controller. The memory systems comprises a memory hub device integrated in a memory module, a set of memory devices coupled to the memory hub device, and a f... | 04/19/2011 |
| 7930469 | System to provide memory system power reduction without reducing overall memory system performance A memory system is provided that provides memory system power reduction without reducing overall memory system performance. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a... | 04/19/2011 |
| 7925824 | System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency A memory system is provided that reduces latency by running a memory channel fully asynchronous from a memory device frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receiv... | 04/12/2011 |
| 7925825 | System to support a full asynchronous interface within a memory hub device A memory system is provided that implements an asynchronous boundary in a memory module. The memory system comprises a memory hub device integrated in a memory module. The memory system also comprises a set of memory devices coupled to the memory hub device. The mem... | 04/12/2011 |
| 7925826 | System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency A memory system is provided that increases the overall bandwidth of a memory channel by operating the memory channel at a independent frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command ... | 04/12/2011 |
| 7913034 | DRAM access command queuing Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecuti... | 03/22/2011 |
| 7913035 | Method and apparatus for address FIFO for high bandwidth command/address busses in digital storage system A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a pointer location of a read pointer. A dynamic random access memory (DRAM) and system are also disclosed in... | 03/22/2011 |
| 7904641 | Processor system using synchronous dynamic memory A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from ... | 03/08/2011 |
| 7899984 | Memory module system and method for operating a memory module A memory module system, a memory module, a buffer device, a memory module printed circuit board, and to a method for operating a memory module is disclosed. In one embodiment, the memory module system includes at least a first, a second, and a third memory module. T... | 03/01/2011 |
| 7899983 | Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated into a memory module, a first memory device data interface integrated that communicates with a first set of me... | 03/01/2011 |
| 7870329 | System and method for optimizing interconnections of components in a multichip memory module An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are... | 01/11/2011 |
| 7865660 | Calibration of read/write memory access via advanced memory buffer Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of da... | 01/04/2011 |
| 7865661 | Configurable high-speed memory interface subsystem A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read... | 01/04/2011 |
| 7861029 | Memory module having buffer and memory ranks addressable by respective selection signal A memory module having a board and a plurality of memory elements on the board which belong to different memory ranks, each memory rank being addressable via a respective selection signal. The memory module additionally includes a memory buffer having a memory rank ... | 12/28/2010 |
| 7849255 | Pseudo-bidimensional randomly accessible memory using monodimensional sequentially-accessiblle memory structure A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configura... | 12/07/2010 |
| 7849256 | Memory controller with ring bus for interconnecting memory clients to memory devices Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality o... | 12/07/2010 |
| 7840748 | Buffered memory module with multiple memory device data interface ports supporting double the memory capacity A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and at least one memory module coupled to the memory controller. In the memory systems, each memory module comprises at l... | 11/23/2010 |
| 7822915 | Memory controller for packet applications A method and apparatus for accessing and storing data in a memory are disclosed. The system includes a memory controller coupled to a memory having locations characterized by banks and lines. The memory controller is configured for storing a data packet with data bu... | 10/26/2010 |
| 7818497 | Buffered memory module supporting two independent memory channels A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memor... | 10/19/2010 |
| 7793038 | System and method for programmable bank selection for banked memory subsystems A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system compris... | 09/07/2010 |
