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"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 8180950 | Apparatus and method to manage information using an optical and holographic data storage medium A hybrid optical and holographic data storage medium is disclosed. In addition, a method is disclosed to manage information using that optical and holographic data storage medium. The method reads information from the optical data storage layer before reading data f... | 05/15/2012 |
| 8051085 | Determining regular expression match lengths A method and apparatus are disclosed for determining the lengths of one or more substrings of an input string that matches a regular expression (regex) The input string is searched for the regex using an non-deterministic finite automaton (NFA), and upon detecting a... | 11/01/2011 |
| 7941585 | Local scratchpad and data caching system A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main reg... | 05/10/2011 |
| 7895390 | Ensuring buffer availability A buffer availability manager ensures that buffers are available before processes write thereto. The buffer availability manager maintains a plurality of register sets corresponding to the plurality of buffers. Each register set comprises a status indicator and a ge... | 02/22/2011 |
| 7853604 | Inline view query rewrite using a materialized view A method allows a query, which contains an inline view, to be rewritten to use a materialized view. The materialized view has an inline view that is equivalent to the inline view of the query. However, the inline view of the materialized view varies textually from t... | 12/14/2010 |
| 7822731 | Techniques for management of information regarding a sequential stream Described are techniques for managing a sequential stream in a data storage system. A front-end component receives a plurality of data operations for a plurality of data portions and determines that the plurality of data portions are associated with a sequential str... | 10/26/2010 |
| 7818489 | Integrating data from symmetric and asymmetric memory Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to b... | 10/19/2010 |
| 7769779 | Reverse name mappings in restricted namespace environments A silo-specific view of the file system is provided to processes running in the silo. Processes can access a file only by uttering the silo-relative name. To determine if access to a file identified by a file ID should be permitted, a list of physical names of the f... | 08/03/2010 |
| 7739442 | Macroscalar processor architecture A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive o... | 06/15/2010 |
| 7716411 | Hybrid memory device with single interface Described is a technology by which a memory controller is a component of a hybrid memory device having different types of memory therein (e.g., SDRAM and flash memory), in which the controller operates such that the memory device has only a single memory interface w... | 05/11/2010 |
| 7624224 | System and method for directly executing code from block-based memory A system, method, and computer program product are provided for directly executing code in block-based memory, which resides in communication with a processor and a controller. Utilizing the controller, a request is received from the processor for a subset of a bloc... | 11/24/2009 |
| 7613868 | Method and system for optimizing the number of word line segments in a segmented MRAM array A method and system for programming and reading a magnetic memory is disclosed. The magnetic memory includes a plurality of selectable word line segments and a plurality of magnetic storage cells corresponding to each word line segment. The method and system include... | 11/03/2009 |
| 7610433 | Memory controller interface A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory (SRAM) memory devices to instead operate using NAND flash and synchronous dynamic random access memory (SDRAM). The system... | 10/27/2009 |
| 7500049 | Providing a backing store in user-level memory In one embodiment, the present invention includes a method for requesting an allocation of memory to be a backing store for architectural state information of a processor and storing the architectural state information in the backing store using an application. In t... | 03/03/2009 |
| 7454556 | Method to program non-JTAG attached devices or memories using a PLD and its associated JTAG interface A method is provided to program a memory device through a JTAG interface of an attached component with programmable logic, wherein the memory device does not have a JTAG interface. Initially, programming hardware to provide for programming of the attached memory is ... | 11/18/2008 |
| 7437497 | Method and apparatus for encoding memory control signals to reduce pin count One embodiment of the present invention provides a system that uses encoded memory control signals to reduce pin count on chips that generate and drive memory control signals. During operation, the system receives encoded memory control signals from a memory control... | 10/14/2008 |
| 7430631 | Access to a wide memory A processing system includes a processor and a physical memory (500) with a single-size memory port (505) for accessing data in the memory. The processor is arranged to operate on data of at least a first data size and a smaller second data size. The f... | 09/30/2008 |
| 7426604 | Virtual output buffer architecture A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination ... | 09/16/2008 |
| 7424571 | Array machine context data memory A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a ... | 09/09/2008 |
| 7421535 | Method for demoting tracks from cache Provided are a method, system, and program for destaging a track from cache to a storage device. The destaged track is retained in the cache. Verification is made of whether the storage device successfully completed writing data. Indication is made of destaged track... | 09/02/2008 |
| 7409488 | Data processing system A data processing system comprises a local probe storage array having a plurality of sensors for reading data from a storage surface. A plurality of data processing elements are mounted on the storage array. Each data processing element is connected to different sen... | 08/05/2008 |
| 7404058 | Method and apparatus for avoiding collisions during packet enqueue and dequeue A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or stat... | 07/22/2008 |
| 7398484 | Memory efficient array transposition via multi pass tiling A schedule can be generated for physically transposing an array such that when the array is transferred from a first memory type to a second memory type, the number of block transfers performed is minimized. The array can be rearranged to ensure that most or all dat... | 07/08/2008 |
| 7386659 | Memory system A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller ... | 06/10/2008 |
| 7386652 | User-configurable pre-recorded memory In a user-configurable pre-recorded memory (UC-PM), a user can select contents he is interested in, and pay copyright fees accordingly. With large capacity, low cost and great integratibility, 3D-M, more particularly 3D-MPM, is suitable for UC-PM. It provides excell... | 06/10/2008 |
| 7383376 | Apparatus and methods for storing data in a magnetic random access memory (MRAM) An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of clock cycles required to store data by eliminating at least one wait state in a transition from a read sta... | 06/03/2008 |
| 7383421 | Cellular engine for a data processing system A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is ut... | 06/03/2008 |
| 7380050 | Parallel data storage device A parallel data storage device includes a data storage medium having a first cluster and a second cluster. The first cluster includes a first patch and the second cluster includes a second patch. The parallel data storage device also includes a first reader for read... | 05/27/2008 |
| 7379442 | Method and apparatus for buffer storage of data packets which are to be transmitted via a connection that has been set up So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ messages to be sent back to ... | 05/27/2008 |
| 7376801 | Power saving data storage circuit, data writing method in the same, and data storage device It is an object to provide, in a data storage circuit for storing data, a power saving data storage circuit and a data writing method in the data storage circuit, and, further, to provide a data storage device. Thus, in the present invention, reading out existing da... | 05/20/2008 |
| 7372713 | Match sensing circuit for a content addressable memory device A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match line, as well as a reference dummy match line. The dummy match line is designed to be evaluated after all... | 05/13/2008 |
| 7370166 | Secure portable storage device In one embodiment of the present invention, a secure storage system includes a removable storage device having a secure storage area for storage of secure data and a public storage area and device port for coupling the removable storage device to a host, the removab... | 05/06/2008 |
| 7370170 | Data mask as write-training feedback flag Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is conver... | 05/06/2008 |
| 7370141 | Memory system A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller ... | 05/06/2008 |
| 7366844 | Data processing system and method for handling castout collisions A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single upda... | 04/29/2008 |
| 7366821 | High-speed memory system A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing ... | 04/29/2008 |
| 7363427 | Memory controller connection to RAM using buffer interface A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the m... | 04/22/2008 |
| 7363423 | Multiple match detection circuit Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR (xi AND xj), where xi=x1, x | 04/22/2008 |
| 7360001 | External card connection device having parameter and command registers wherein device is connectable to a host device An external connection device is to connectable to a host device. The host device includes transmission means for transmitting, to the external connection device, a parameter and an operation control command indicating a command for performing operation control of t... | 04/15/2008 |
| 7358990 | Image-taking apparatus capable of saving image data files in folder on recording medium An image-taking apparatus preferable for saving image data in folders as desired by a user for each scene or date of image-taking is disclosed. The image-taking apparatus of the present invention comprises an image processing circuit which creates image data files b... | 04/15/2008 |
