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"Flight by machines heavier than air is unpractical and insignificant, if not utterly impossible."
Simon Newcomb, astronomer ; Said in 1902, less than two years before the first flight at Kitty Hawk
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| Number | Title | Issue Date |
| 7464203 | Method of validating plurality of data during serial communication using a dual path across a single serial link A method and apparatus is provided for validating a plurality of variable data transmitted in an automobile, comprising generating a control copy and a redundant copy of the variable data, calculating a pre-transmittal cross-check measure using the redundant copy of... | 12/09/2008 |
| 7380031 | Hybrid data distribution systems A hybrid data distribution system includes a modulator coupled to an analog device, one or more processors coupled to the modulator, and a database coupled to the one or more processors. The database is configured to store encoded data. The system also includes an E... | 05/27/2008 |
| 7266623 | Portable computer A portable computer can be selectively configured with a first hard disk or a second hard disk. The portable computer includes a controller, an interface connector, and a second interface adapter. The controller includes a first interface controlling unit and a seco... | 09/04/2007 |
| 7245173 | Method to reduce integrated circuit power consumption by using differential signaling within the device A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling comprises a pair of coupled, symmetrically opposite and operatively dependent electronic signals each drive... | 07/17/2007 |
| 7240133 | Reduced-area architecture for padded-protocol interface A data converter for a padded protocol interface performs, on a first data sample, decoding operations requiring data from second and third data samples, while buffering the second data sample without buffering the third data sample. A state machine controlling the ... | 07/03/2007 |
| 7230495 | Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V... | 06/12/2007 |
| 7227918 | Clock data recovery circuitry associated with programmable logic device circuitry A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholl... | 06/05/2007 |
| 7212054 | DLL with adjustable phase shift using processed control signal Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector... | 05/01/2007 |
| 7208993 | Input current leakage correction for multi-channel LVDS front multiplexed repeaters A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of the circuit exceeds the supply voltage. The LVDS repeater includes a multiplexor having a plurality of d... | 04/24/2007 |
| 7143176 | Data communication with a protocol that supports a given logical address range A method for copying data over a network operating in accordance with a protocol, such as the ESCON protocol, that supports a given logical address range includes establishing a logical path over the network from a primary storage system to a secondary storage syste... | 11/28/2006 |
| 7124056 | Information transmission device for construction machine An information transmitting device to supply operation data of a machine as needed and without unnecessary data. The information transmitting device includes information control device 4, remote base station 9, transmission means, e.g. communication sa... | 10/17/2006 |
| 7091760 | DLL with adjustable phase shift using processed control signal Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector... | 08/15/2006 |
| 7075365 | Configurable clock network for programmable logic device In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmenta... | 07/11/2006 |
| 7071743 | Programmable phase-locked loop circuitry for programmable logic device A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections... | 07/04/2006 |
| 7046070 | LVDS switch control device for a portable apparatus An LVDS switch control device for a portable apparatus is disclosed, which has an LVDS transducer, which transforms the image information for the portable apparatus into LVDS signals; a buffer receiving the LVDS signals transmitted by the connection pedestal as the ... | 05/16/2006 |
| 7019570 | Dual-gain loop circuitry for programmable logic device A loop circuit (PLL or DLL) uses a dual-gain voltage-controlled component (VCO or VCDL) to achieve a phase (and frequency) lock with reduced jitter. A coarse control feedback path includes a detector for achieving an approximate lock. This path operates over a wide ... | 03/28/2006 |
| 6956920 | Apparatus and method for low power routing of signals in a Low Voltage Differential Signaling system A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response ... | 10/18/2005 |
| 6924678 | Programmable phase-locked loop circuitry for programmable logic device A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections... | 08/02/2005 |
| 6925531 | Multi-element storage array A self-contained data storage module receives a data request conforming to a first standard. The data request is translated into a second standard. At least one of the storage devices mounted on a board within the data storage module is identified. The translated da... | 08/02/2005 |
| 6868463 | Audio data recording apparatus and audio data sending/receiving method of the apparatus The apparatus and method for transferring audio data to a data recorder adopting a personal computer bus to receive audio data enters into data communication mode over a bus without conducting preparation steps for transferring data when a record request is received... | 03/15/2005 |
| 6769034 | Virtual AV network building device, virtual AV network building method, and recorded medium on which program concerning virtual AV network building method is recorded The present invention relates to an AV network construction apparatus A, comprising: a 1394 link 10 for connecting lines employing an interface of IEEE1394 standard, an information receiving/transmitting means 11, a protocol processing means 12,... | 07/27/2004 |
| 6757764 | Method and apparatus for transferring information using a constant frequency An information transfer apparatus including an information source connected to an information to constant frequency converter, a transmitter connected to the information to constant frequency converter, a receiver linked to the transmitter, and a constant frequency ... | 06/29/2004 |
| 6687775 | Dual purpose serial/parallel data transfer device for peripheral storage device A peripheral storage device system and a data transfer device for use in a peripheral storage device system are disclosed, which provide for selective information transfer between a peripheral storage device, such as a disk drive, a CDROM drive, or a tape... | 02/03/2004 |
| 6633921 | Intelligent network connecting apparatus An intelligent network connecting apparatus for serving as a terminal of network includes a female Ethernet connector, female USB connector, converting means, and auto-detecting switch. While a computer couples with the female Ethernet connector, signals ... | 10/14/2003 |
| 6378007 | Data encoding scheme In a tape drive, or other storage device, used for storing computer data, both record data and record structure information such as file marks are encoded with codewords to form an encoded data stream. Of the fixed number of possible fixed-length codeword... | 04/23/2002 |
| 6378011 | Parallel to serial asynchronous hardware assisted DSP interface Parallel data is serialized and transmitted and asynchronous data is received and placed into parallel bytes using a hardware assisted interface. The interface can be driven with very little overhead to the DSP. Additional timing registers and enhanced da... | 04/23/2002 |
| 6345328 | Gear box for multiple clock domains A gear box module or circuit can act as an interface for transferring data from a first clock domain to a second clock domain. The gear box circuit uses a level sensitive memory element coupled to an input selection circuit to receive data from logic in t... | 02/05/2002 |
| 6324611 | Physical layer interface and method for arbitration over serial bus using digital line state signals A physical layer interface for a serial bus includes a controller for producing parallel data representing a near-end line state of the serial bus. A line transmitter is connected to the controller for converting the parallel data therefrom into serial da... | 11/27/2001 |
| 6314479 | Universal multi-pin plug and display connector for standardizing signals transmitted between a computer and a display for a PC theatre interconnectivity system An interconnectivity scheme for a PC Theatre system includes the use of compatible plug and display connectors on both the display and the host computer. Audio/video signals received by either the display or the computer may be processed by the computer a... | 11/06/2001 |
| 6308229 | System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic An asynchronous FIFO using Asynchronous NULL Convention LOGIC (NCL) to facilitate interfacing between multiple non-synchronous systems with a minimum of design and verification. Multiple interfaces, configurations, means for minimizing latency, and capabi... | 10/23/2001 |
| 6266727 | Isochronous data pipe for managing and manipulating a high-speed stream of isochronous data flowing between an application and a bus structure An isochronous data pipe provides a bidirectional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any ... | 07/24/2001 |
| 6199135 | Source synchronous transfer scheme for a high speed memory interface Data transfer scheme wherein data transfer rates can be effectively doubled with no increase in the clock speed of the interface. This is accomplished by allowing more than one data transfer to occur on a single clock cycle. This transfer scheme increases... | 03/06/2001 |
| 6128673 | Method and apparatus for communication and translation of a plurality of digital protocols A digital protocol translator including a first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, the first protocol circuitry including a first controller. The translator further includes a second protocol ... | 10/03/2000 |
| 6128678 | FIFO using asynchronous logic to interface between clocked logic circuits An asynchronous FIFO using Asynchronous NULL Convention LOGIC (NCL) to facilitate interfacing between multiple non-synchronous systems with a minimum of design and verification. Multiple interfaces, configurations, means for minimizing latency, and capabi... | 10/03/2000 |
| 6044422 | Modem for connection to a telephone line through a either portable computer connector or a docking station via an isolation circuit A laptop computer contains a built-in modem and has a phone jack for connection to a telephone line while the computer is being operated in a stand-alone mode. A docking station into which the laptop computer may be docked allows the combined unit to be o... | 03/28/2000 |
| 5987543 | Method for communicating digital information using LVDS and synchronous clock signals Video data is communicated in a computer system using LVDS signaling. To maintain minimum setup time requirements, video data is translated to LVDS data streams using a TTL-to-LVDS converter (84) which clocks data at the rising edge of a pixel clock signa... | 11/16/1999 |
| 5931929 | Modem for connection to a telephone line through a either portable computer connector or a docking station A laptop computer contains a built-in modem and has a phone jack for connection to a telephone line while the computer is being operated in a stand-alone mode. A docking station into which the laptop computer may be docked allows the combined unit to be o... | 08/03/1999 |
| 5898886 | Multimedia devices in computer system that selectively employ a communications protocol by determining the presence of the quaternary interface A computer system is presented having various peripheral devices coupled to a PCI local bus (i.e., an expansion bus), a subset of the peripheral devices having quaternary interfaces configured to communicate via quaternary signals conveyed upon the PCI lo... | 04/27/1999 |
| 5862412 | Apparatus for converting document data into bit map data and compressing display image formed by combining the bit map data and image data The invention provides a character and picture data compression apparatus which can collectively compress document data of the character code form and still picture data and moving picture data of the bit map form. A conversion section converts document d... | 01/19/1999 |
| 5748984 | Ad converting apparatus including holding means indicating whether or not data after AD conversion has been previously used An AD converting apparatus which is provided with a data update flag 3b for storing a first value ("1") when an analog signal is newly converted by an AD converter 1 to digital data and is stored into a data register 3a, and for storing a second value ("0... | 05/05/1998 |
