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"Flight by machines heavier than air is unpractical and insignificant, if not utterly impossible."
Simon Newcomb, astronomer ; Said in 1902, less than two years before the first flight at Kitty Hawk
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| Number | Title | Issue Date |
| 8166217 | System and method for reading and writing data using storage controllers A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes convers... | 04/24/2012 |
| 8131897 | Semiconductor memory device inputting and outputting a plurality of data length formats and method thereof A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a first processor configured to exchange data with a first data length format, a second processor configured to exchange data with a second data length... | 03/06/2012 |
| 8073999 | Data input-output control apparatus A system controller is presented that controls an output format of data according to a data congestion status of the data and then outputs the data over an output bus. Specifically, if there is data congestion, the system controller changes the format of the data to... | 12/06/2011 |
| 7958288 | Semiconductor storage device and method of controlling the same A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controll... | 06/07/2011 |
| 7958287 | Semiconductor storage device and method of controlling the same A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controll... | 06/07/2011 |
| 7890679 | Data generator for generating data of arbitrary length A data generator provides faster data than before. A parallel data generator 18 provides first data having four or five effective data width according to a divided clock DCLK. A bit width adjuster 20 having a FIFO memory receives the first parallel dat... | 02/15/2011 |
| 7877530 | Bus width negotiation There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data sto... | 01/25/2011 |
| 7739430 | Semiconductor integrated circuit A semiconductor integrated circuit provided with an (m×n)-bit output mode and an n-bit output mode and including a set of (m×n) I/O portions 103 for outputting signals to the outside, wherein data with a bus width of (m×n) bits are selected by a set of sel... | 06/15/2010 |
| 7624211 | Method for bus width negotiation of data storage devices There is provided a method and apparatus for bus width negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable da... | 11/24/2009 |
| 7620756 | Method and apparatus for updating wide storage array over a narrow bus A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m | 11/17/2009 |
| 7574541 | FIFO sub-system with in-line correction A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfa... | 08/11/2009 |
| 7433980 | Memory of and circuit for rearranging the order of data in a memory having asymmetric input and output ports Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an out... | 10/07/2008 |
| 7433927 | Network system, network control method, and signal sender/receiver A network system connects with processes P1 to P5 that can mutually send and receive a broadcast message specified with no destination and a message specified with a specific process portion and change their states to parent or child processes. For exa... | 10/07/2008 |
| 7421479 | Network system, network control method, and signal sender/receiver A network system connects with processes P1 to P5 that can mutually send and receive a broadcast message specified with no destination and a message specified with a specific process portion and change their states to parent or child processes. For exa... | 09/02/2008 |
| 7418530 | Storage device and method for controlling storage device packet size The present invention variably controls the packet size that is used within a storage device in accordance with the communication environment outside the storage device. The storage device comprises a CHA that controls data transfers with a host and a DKA that contr... | 08/26/2008 |
| 7409479 | Semiconductor integrated circuit When needing to make write accesses to both upper and lower sides of a counter in a timer, a CPU accesses the lower side last, and accesses the lower side first when needing to make read accesses thereto. The timer stores data of the data bus in the write buffer at ... | 08/05/2008 |
| 7376767 | Distributed buffering system having programmable interconnecting logic and applications thereof A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data bloc... | 05/20/2008 |
| 7376777 | Performing an N-bit write access to an M×N-bit-only peripheral A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a wr... | 05/20/2008 |
| 7376780 | Protocol converter to access AHB slave devices using the MDIO protocol A method for communicating between a first bus and a second bus is disclosed. The method generally includes the steps of (A) recognizing a read operation code in a read frame (i) received from the first bus and (ii) communicated with a first-bus protocol, (B) initia... | 05/20/2008 |
| 7363402 | Data communications architecture employing parallel SERDES channels A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains var... | 04/22/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7350001 | Method and apparatus for automatic word length conversion Methods and Apparatuses are provided for automatically converting a word length of sample data being transmitted over a serial link. A serial interface transmits and/or receives one or more data words comprising digital signals, a bit clock synchronizes transmission... | 03/25/2008 |
| 7342520 | Method and system for multilevel serializer/deserializer A serial bit transparent data transferring technique eliminating the bit ambiguity problem of the standard time-division multiplexing/demultiplexing architecture without introduction of any extra latency. A serializer multiplexer converts input parallel data words i... | 03/11/2008 |
| 7337260 | Bus system and information processing system including bus system In a bus connection circuit for connecting buses having different bit widths, number of clock cycles can be reduced, and hardware amount can be reduced. The bus connection circuit connects buses of mutually different bit widths having control lines and data lines co... | 02/26/2008 |
| 7337272 | Method and apparatus for caching variable length instructions An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary positi... | 02/26/2008 |
| 7328299 | Interface for compressed data transfer between host system and parallel data processing system An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the interface apparatus to be programmed to operate as a transmitter or a receiv... | 02/05/2008 |
| 7325098 | System and method for non-destructive handling of outsized words by a cache An extended data queue is added to the cache circuitry of a processor to handle extended data when the processor operates on a different architecture than the system it resides on. The extended data for each word coming into the processor is stored in the queue. If ... | 01/29/2008 |
| 7319702 | Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment with a current segment or delay the fragment to combine with a next segment for alignment of data. A buf... | 01/15/2008 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7308536 | System bus read data transfers with data ordering control bits A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the o... | 12/11/2007 |
| 7308514 | Configuring a communication link interface Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of... | 12/11/2007 |
| 7304883 | Semiconductor integrated circuit In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit 20A is dedicated to a first functional block having one first write port section 21AW and two first read port sections 21AR1 | 12/04/2007 |
| 7293123 | Asymmetric data path media access controller A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ... | 11/06/2007 |
| 7287148 | Unified shared pipeline allowing deactivation of RISC/DSP units for power saving An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and t... | 10/23/2007 |
| 7286067 | Appliance with communication protocol emulation An appliance includes a physical interface for communication according to a broad protocol and two functional components. The first functional component communicates via the physical interface. The second functional component includes a functional module adapted to ... | 10/23/2007 |
| 7280539 | Data driven type information processing apparatus In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a funct... | 10/09/2007 |
| 7280051 | Transmission and reception of a decomposed digitized signal A voice signal is transmitted in an MOST network on a single channel. The width of the transmitted voice data words is preferably up to 14 bits, and each voice data word is transmitted into successive clock periods of the MOST network, in a byte that includes seven ... | 10/09/2007 |
| 7281066 | Memory access system including support for multiple bus widths A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coup... | 10/09/2007 |
| 7278060 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 10/02/2007 |
