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| Number | Title | Issue Date |
| 8161210 | Multi-queue system and method for deskewing symbols in data streams A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a deskew unit for each data stream, each of which inclu... | 04/17/2012 |
| 8060672 | Event signaling between peripheral modules and a processing unit There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral module and a processing unit by means of a system bus. In this case the... | 11/15/2011 |
| 8055822 | Multicore processor having storage for core-specific operational data An integrated circuit includes a plurality of processor cores and a readable non-volatile memory that stores information expressive of at least one operating characteristic for each of the plurality of processor cores. Also disclosed is a method to operate a data pr... | 11/08/2011 |
| 7979611 | Multi-protocol serial interface apparatus and system-on-chip apparatus including the same A multi-protocol serial interface (MPSI) apparatus can include a controller circuit that is configured to receive information about a type of MPSI utilized for data transfer and that is configured to control a format of the data transfer and input/output timing asso... | 07/12/2011 |
| 7970964 | Methods and systems to accomplish variable width data input Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each ... | 06/28/2011 |
| 7953910 | All-in-one personal computer with external video input An AIO PC has its LVDS link or interface, between the mother board and the LCD, modified by the insertion of an LVDS Switch which can connect to a second LVDS source such as LCD controller which takes its input from a socket mounted on the housing of the AIO PC. The... | 05/31/2011 |
| 7949806 | Apparatus and method to provide an operation to an information storage device including protocol conversion and assigning priority levels to the operation A method to provide an operation to an information storage device is disclosed. The method supplies an information storage device and a protocol conversion device capable of receiving an operation in a first communication protocol comprising a variable attribute, an... | 05/24/2011 |
| 7904620 | Data transmission system with protocol conversion The invention disclosed a data transmission system, comprising a first conversion module provided on the host side, used for converting USB data into data in format which may be transmitted by a data transmission module and for converting data in format which may be... | 03/08/2011 |
| 7870316 | System and method for providing an inline data conversion for multiplexed data streams A computing system having an apparatus for providing an inline data conversion processor. The inline data conversion processor includes a host processor interface, a network interface, a peripheral interface, and a packer stream address for defining a data transform... | 01/11/2011 |
| 7853741 | Tunneling SATA targets through fibre channel A system for enabling SATA drives to be utilized in FC SANs is disclosed. To send SATA FISs to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fiber Channel Attached SATA Tunneling (FAST) RAID controller,... | 12/14/2010 |
| 7840726 | System and method for identifying and transferring serial data to a programmable logic device A system and method is disclosed for programming a field programmable gate array. The system involves the recognition of the next following bit sequence to be transmitted to the FPGA through a general purpose input output device. Once the bit sequence is identified,... | 11/23/2010 |
| 7783801 | KVM console cable and multi-computer system using the same The invention provides KVM console cables, comprising a video connector, a first console connector, a second console connector, a third console connector, a combined connector, and a transmission line. The video connector is utilized to connect to a video monitor. T... | 08/24/2010 |
| 7711875 | High speed on-chip serial link apparatus A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. Th... | 05/04/2010 |
| 7668988 | Data bus inversion detection mechanism A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comp... | 02/23/2010 |
| 7587536 | Method and apparatus for distributing USB hub functions across a network A method and related apparatuses for data transmission between a host computer and one or a plurality of USB compliant peripheral devices over a data communications network is provided which operates in the presence of transmission delays greater than that normally ... | 09/08/2009 |
| 7577777 | Computer system providing endian information and method of data transmission thereof A computer system providing endian information and a method of data transmission thereof are disclosed. The method of data transmission in the computer system of the present invention comprises: reading endian information stored in a base address register of periphe... | 08/18/2009 |
| 7549000 | Apparatus and method for generating bitstream of S/PDIF data in HDMI An apparatus and method for regenerating S/PDIF data is disclosed. The apparatus includes a buffer for buffering sample words of the data units; a decision unit for receiving control words of the data units and outputting a selected control word according to a curre... | 06/16/2009 |
| 7546401 | Byte to byte alignment of multi-path data Methods and apparatus that may be utilized in an effort to ensure bytes of data sequentially received on multiple single-byte data paths with properly aligned when presented on a multi-byte interface are provided. A sufficient number of bytes received each channel m... | 06/09/2009 |
| 7490181 | Data reproducing apparatus for transforming external input signal and method thereof A DVD reproducing device is capable of being connected to a certain external electronic device. The DVD reproducing device includes an external input receiving unit connected with the external electronic device to receive an external input signal from the external e... | 02/10/2009 |
| 7467244 | Connecting a computer program and a peripheral device using a first communication protocol through an interconnect using a second communication protocol A device and method for electronic data conversion is provided. Data according to IEEE 1394 format and protocol is received and converted to USB format and protocol and supplied to a system configured to receive data according to USB format and protocol. ... | 12/16/2008 |
| 7444442 | Data packing in a 32-bit DMA architecture A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packin... | 10/28/2008 |
| 7441063 | KVM system for controlling computers and method thereof A system for connecting a console device to computers comprising a graphic user interface menu apparatus for controlling the computers. The system comprises a user-side circuit, a central crosspoint switch, a plurality of computer-side circuits, a menu generating un... | 10/21/2008 |
| 7433980 | Memory of and circuit for rearranging the order of data in a memory having asymmetric input and output ports Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an out... | 10/07/2008 |
| 7433981 | System and method for using co-processor hardware to accelerate highly repetitive actions An architecture is described, wherein an operation unit, such as an arithmetic unit, is used for performing a variety of repetitive tasks. The present invention includes embodiments and related methods for power and computationally efficiency in performing repetitiv... | 10/07/2008 |
| 7430624 | High speed on-chip serial link apparatus and method A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. Th... | 09/30/2008 |
| 7430564 | Performance information reproducing apparatus and method and performance information reproducing program There is provided a performance information reproducing apparatus that is capable of realizing desired synchronized reproduction of a plurality of types of data, such as music and images with ease. An external storage device stores a musical tone data file, in which... | 09/30/2008 |
| 7418344 | Removable computer with mass storage The present invention provides a detachable add-on card unit to a host system that combines mass storage capability and a processor on the same card. The card can receive data from the host, process the data, and store it in processed form, as well as the reverse pr... | 08/26/2008 |
| 7415323 | Control apparatus and program for vehicles, and method for developing the program A vehicle control apparatus comprises: a computer operable to execute a control program, a first memory storing the control program, and a second memory storing the produced data. The control program includes: a platform program for inputting data from a hardware de... | 08/19/2008 |
| 7409479 | Semiconductor integrated circuit When needing to make write accesses to both upper and lower sides of a counter in a timer, a CPU accesses the lower side last, and accesses the lower side first when needing to make read accesses thereto. The timer stores data of the data bus in the write buffer at ... | 08/05/2008 |
| 7409473 | Off-chip data relocation The on-chip copy process is extended so that the data may be copied between two blocks that may be on different chips, different planes on the same chip, or the same plane of the same chip. More specifically, the methods described here provide a single data copying ... | 08/05/2008 |
| 7406101 | System and method for providing on-chip delay measurements in serializer / deserializer systems A system and method is provided for making highly accurate data propagation delay measurements in a serializer/deserializer (SERDES) integrated circuit. The invention detects a selected special character when the special character is present at the input of a transm... | 07/29/2008 |
| 7404015 | Methods and apparatus for processing packets including accessing one or more resources shared among processing engines Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets... | 07/22/2008 |
| 7404019 | Method and apparatus for endianness control in a data processing system A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect... | 07/22/2008 |
| 7401170 | Communication system, and master apparatus and slave apparatus used in the same, and communication method This communication system performs serial data communication between a master apparatus and a plurality of the slave apparatus via a data transmission line. The master apparatus generates, by using a controller, a serial conversion order control signal for controlli... | 07/15/2008 |
| 7398334 | Circuit for and method of realigning data A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and cont... | 07/08/2008 |
| 7395363 | Methods and apparatus for multiple bit rate serial communication Symbols are prepared for transmission by representing each bit of the symbols by a cluster of consecutive bits, identical to the bit, in a transmission bit sequence. The transmission bit sequence is transmitted at a particular bit rate. A reception bit sequence of r... | 07/01/2008 |
| 7392333 | Fibre channel environment supporting serial ATA devices A system and method in a fibre channel environment supporting serial ATA devices. In one embodiment, the system and method includes a network having a plurality of servers and a plurality of fiber-channel devices connected to each other through the network. In anoth... | 06/24/2008 |
| 7380141 | Transferring data without completing a boot process A computer system including a power supply; a connector to be connected with a detachable storage medium; an auxiliary memory; a selection input part to generate a storage function processing signal to store data of the storage medium to the auxiliary memory accordi... | 05/27/2008 |
| 7376763 | Method for transferring data from a memory subsystem to a network adapter by extending data lengths to improve the memory subsystem and PCI bus efficiency A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a c... | 05/20/2008 |
| 7376021 | Data output circuit and method in DDR synchronous semiconductor device Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted ... | 05/20/2008 |
