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"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 8171189 | Semiconductor apparatus A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buf... | 05/01/2012 |
| 8108575 | Methods of multi-server application synchronization without stopping I/O A method according to one embodiment includes receiving a request to perform a backup of data associated with an application running on multiple servers; calculating a time value based on communications with the servers, the time value calculation including at least... | 01/31/2012 |
| 8095707 | Method for synchronization of peripherals with a central processing unit in an embedded system A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O p... | 01/10/2012 |
| 8082375 | Noise-tolerant data communication system This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer a... | 12/20/2011 |
| 7877529 | Low overhead, data transparent synchronization of streaming serial data Synchronization management is provided for a continuous serial data streaming application wherein the serial data stream includes a plurality of consecutive, identical-length segments of consecutive serial data bits. Synchronization management bits are provided in e... | 01/25/2011 |
| 7861018 | System for transmitting data between transmitter and receiver modules on a channel provided with a flow control link A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver modu... | 12/28/2010 |
| 7769928 | Data storage system having CPUs adapted to perform a second atomic operation request prior to completion of a first atomic operation request A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests,... | 08/03/2010 |
| 7644208 | Serial transmission system with a return signal generator from the farthest terminal to synchronize return signals/data from the farthest terminal with any specified intervening terminals A terminal of a plurality of terminals that is located at the farthest position from a host has a return signal generator section, the return signal generator section transmits a return signal at a timing when data transmitted from the host to the terminals arrives ... | 01/05/2010 |
| 7617339 | Serial interface circuit for data transfer A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral registers and the first circuit; the first circuit including mirror reg... | 11/10/2009 |
| 7613853 | Output buffer circuit capable of synchronous and asynchronous data buffering using sensing circuit, and method and system of same An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and asynchronous applications, comprising: a pair of flip-flops receiving compleme... | 11/03/2009 |
| 7581045 | Method, system, and article of manufacture for mapping programming interfaces Provided are a method, system, and article of manufacture for mapping programming interfaces. A synchronous request for reading data is received. An asynchronous request to fill selected buffers of a plurality of buffers is sent. The synchronous request is responded... | 08/25/2009 |
| 7552256 | Network device interface for digitally interfacing data channels to a controller via a network A communications system and method are provided for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the contro... | 06/23/2009 |
| 7543090 | Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed ve... | 06/02/2009 |
| 7539793 | Synchronized multichannel universal serial bus The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external sourc... | 05/26/2009 |
| 7437491 | Clock and data recovery wherein an FB-DIMM is connected to signal path and null and sync frames control the FB-DIMM Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frame... | 10/14/2008 |
| 7430660 | Data transmission apparatus, system and method, and image processing apparatus A data transmission system where an image providing device and a printer are directly connected by a 1394 serial bus, a command is sent from the image providing device to the printer, then a response to the command is returned from the printer to the image providing... | 09/30/2008 |
| 7424559 | Input/output upper and lower byte control device using nonvolatile ferroelectric register An input/output byte control device using a nonvolatile ferroelectric register can maintain compatibility with various memories by selectively controlling bytes of input/output data. Since bytes of input/output data are selectively activated, the compatibility can b... | 09/09/2008 |
| 7409474 | Method and system for rate adaptation A media access controller, which includes an output buffer and a clock controller, is provided. The output buffer includes a first and second clock input. The first clock is configured to control data input into the buffer and the second clock is configured to contr... | 08/05/2008 |
| 7406548 | Systems and methods for responding to a data transfer Systems and methods for responding to a data transfer are disclosed. One embodiment comprises a method that includes the following steps: determining a sustainable data transfer rate for data transfers to/from an external memory medium, acquiring a data stream, tran... | 07/29/2008 |
| 7398344 | Plural interfaces in home network with first component having a first host bus width and second component having second bus width Universal network interfaces for a home network connect disparate components to the network, such as relatively complex components (TVs, computers) and relatively simple components (audio boom boxes). ... | 07/08/2008 |
| 7386659 | Memory system A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller ... | 06/10/2008 |
| 7383372 | Bus system, station for use in a bus system, and bus interface The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring signals. The bus is arranged to operate according to a protocol in which said first station repeatedly sends requests for data to the second stati... | 06/03/2008 |
| 7370141 | Memory system A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller ... | 05/06/2008 |
| 7367029 | Method and system for handling data Handling data at one of a plurality of components, wherein the plurality of components includes at least a sink component and a source component. The source component transfers data to the sink component, and the sink component accesses an obtained data type handler... | 04/29/2008 |
| 7366943 | Low-latency synchronous-mode sync buffer circuitry having programmable margin Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference clock signal, marked by the assertion of a periodic sync signal. The ... | 04/29/2008 |
| 7363440 | System and method for dynamically accessing memory while under normal functional operating conditions A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maint... | 04/22/2008 |
| 7356622 | Method and apparatus for managing and formatting metadata in an autonomous operation conducted by a third party An apparatus, system, and method for managing and formatting data in an autonomous data transfer operation are provided. An initialization module is configured to prepare metadata corresponding to a data source. A loader loads autonomous operation instructions corre... | 04/08/2008 |
| 7353299 | Method and apparatus for managing autonomous third party data transfers An apparatus, system, and method for managing and formatting data in an autonomous data transfer operation are provided. An initialization module is configured to prepare metadata corresponding to a data source. A loader loads autonomous operation instructions corre... | 04/01/2008 |
| 7342977 | Serial data transmitter with bit doubling A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of... | 03/11/2008 |
| 7340313 | Monitoring device for monitoring internal signals during initialization of an electronic circuit The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for forwarding internal data (105) in the electronic circuit unit (101) and at least one... | 03/04/2008 |
| 7340668 | Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words writte... | 03/04/2008 |
| 7340633 | Method for automatically detecting the clock frequency of a system clock pulse for the configuration of a peripheral device The present invention provides a method for automatic identification of the clock frequency of a system clock (15) for the configuration of a peripheral device (12), having the following steps: generation of a secondary clock (16) at a predeterm... | 03/04/2008 |
| 7334148 | Optimization of integrated circuit device I/O bus timing The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting... | 02/19/2008 |
| 7330488 | System, method, and article of manufacture for synchronizing time of day clocks on first and second computers A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, r... | 02/12/2008 |
| 7318075 | Enhanced tabular data stream protocol Systems and methodologies are provided as part of a computing environment that implements an enhanced tabular data stream (TDS) protocol. Such enhanced TDS protocol can mitigate synchronization inconsistencies between client and servers, improve robustness of the da... | 01/08/2008 |
| 7313210 | System and method for establishing a known timing relationship between two clock signals A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transpor... | 12/25/2007 |
| 7305501 | Portable computer system having LCD monitor for selectively receiving video signals from external video signal input from external computer A portable computer system includes a portable computer equipped with a graphic chip, and an LCD monitor receiving a video signal from the graphic chip and displaying the video signal. The portable computer system further includes an external video signal input part... | 12/04/2007 |
| 7302505 | Receiver multi-protocol interface and applications thereof A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The... | 11/27/2007 |
| 7302450 | Workload scheduler with resource optimization factoring A workload scheduler supporting an efficient distribution and balancing of the workload is proposed. The scheduler maintains (383-386) a profile for each job; the profile (build using statistics of previous executions of the job) defines an estimated u... | 11/27/2007 |
| 7287105 | Asynchronous-mode sync FIFO having automatic lookahead and deterministic tester operation Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer control logic configured for reading a selected number of the buffer entri... | 10/23/2007 |
