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Hands free towel carrying system
A hands free towel carrying system for coupling a towel to a user to prevent loss, theft or contamination.
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| Number | Title | Issue Date |
| 8055820 | Apparatus, system, and method for designating a buffer status reporting format based on detected pre-selected buffer conditions An apparatus, system and method for increasing buffer status reporting efficiency and adapting buffer status reporting according to uplink capacity. User equipment is configured a monitor a usage of a plurality of buffers, detect one of a plurality of pre-selected c... | 11/08/2011 |
| 8001297 | Dynamic adjusting send rate of buffered data Systems and methods for intermediate buffering of data for the purpose of controlling its delivery to the consumer. The systems and methods for buffering data can arbitrate between the incoming data flow from the generating component and the outgoing data flow to th... | 08/16/2011 |
| 7921242 | Fibre channel elastic FIFO delay controller and loop delay method having a FIFO threshold transmission word adjuster for controlling data transmission rate In a circuit coupled to a port of a network having a loop architecture, a read/write pointer controller provides a read and a write pointer to track transmission words stored in a FIFO array. The read/write pointer controller also provides a FIFO level indicator to ... | 04/05/2011 |
| 7836231 | Buffer control method and device thereof A buffer control method for controlling packets to be stored in a buffer having a data region and a command queue region. First, the number of the packets that can be stored in the data buffer is determined. Then, a count value representing the remained capacity of ... | 11/16/2010 |
| 7739428 | Memory control apparatus and memory control method For an electronic apparatus in which data is transferred between a plurality of processing devices and a memory, a technique is provided which prevents the data transfer from being restricted and allows the processing devices to operate efficiently. The order of pri... | 06/15/2010 |
| 7721026 | Interface controller, method for controlling read access, and information processing apparatus provided with the interface controller An interface controller connected to a read request device which performs a read request to a storage device stored with data, includes a receiving buffer which stores a read response of said storage device with respect to the read request sent from said read reques... | 05/18/2010 |
| 7698481 | Fibre channel elastic FIFO delay controller and loop delay method having a FIFO threshold transmission word adjuster for controlling data transmission rate In a circuit coupled to a port of a network having a loop architecture, a read/write pointer controller provides a read and a write pointer to track transmission words stored in a FIFO array. The read/write pointer controller also provides a FIFO level indicator to ... | 04/13/2010 |
| 7689742 | Data output method, data output apparatus and computer program product A data output apparatus checks data accumulated state in the accumulating unit at a preset check interval, and changes at least one setting among an initial accumulation amount to be used as a basis for starting to output the data accumulated in the accumulating uni... | 03/30/2010 |
| 7653766 | Time-gap defect detection apparatus and method A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corre... | 01/26/2010 |
| 7441055 | Apparatus and method to maximize buffer utilization in an I/O controller An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates... | 10/21/2008 |
| 7437492 | Method and system for data compression and compression estimation in a virtual tape library environment A method and system for efficiently storing and transferring data in a virtual tape library environment is disclosed. Data is written to a virtual tape library that emulates a physical tape library. Data stored in the virtual tape library may be compressed and an es... | 10/14/2008 |
| 7425961 | Display panel driver unit To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port RAM without reduction in an operation speed. A reservation buf... | 09/16/2008 |
| RE40497 | Communication system which dynamically switches sizes of sample buffer between first size for quick response time and second size for robustness to interrupt latency An apparatus for and method of implementing a novel buffer ba full duplex communication system is disclosed. The disclosed invention is particularly useful in native sign processing systems wherein heavy contention of processor resources typically exist, such as in ... | 09/09/2008 |
| 7424566 | Method, system, and apparatus for dynamic buffer space allocation An interconnect apparatus provides for the buffering of information in respective transaction buffers according to transaction type. An additional buffer is dynamically assignable to one of the transaction buffers where additional capacity is required by that transa... | 09/09/2008 |
| 7424565 | Method and apparatus for providing efficient output buffering and bus speed matching An interconnect apparatus includes a transaction packet buffer and control logic. The control logic can be operable sequentially to write transaction packets for transmission to the transaction packet buffer and to transmit the buffered transaction packets in sequen... | 09/09/2008 |
| 7415580 | System for determining the position of an element in memory A system for determining a position of an element in memory comprising a memory queue with a plurality of separate entries and propagate and generate logic in communication with the memory queue such that the propagate and generate logic is operable to inspect each ... | 08/19/2008 |
| 7409474 | Method and system for rate adaptation A media access controller, which includes an output buffer and a clock controller, is provided. The output buffer includes a first and second clock input. The first clock is configured to control data input into the buffer and the second clock is configured to contr... | 08/05/2008 |
| 7404017 | Method for managing data flow through a processing system A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus. ... | 07/22/2008 |
| 7391766 | Packet unstopper system for a parallel packet switch A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ... | 06/24/2008 |
| 7380030 | Method and system for using an in-line credit extender with a host bus adapter A storage area network (“SAN”) and a system is provided. The SAN includes, a host bus adapter operationally coupled with a credit extender, wherein the credit extender receives frames from a Fibre Channel network and sends the received frames to the HBA based on... | 05/27/2008 |
| 7373467 | Storage device flow control A method for allocating data write credits for a storage device includes gathering requests for the data write credits from a plurality of data sources and assembling the plurality of data sources in a prioritized list. The method also includes removing lowest prior... | 05/13/2008 |
| 7370133 | Storage controller and methods for using the same In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later ... | 05/06/2008 |
| 7370126 | System and method for implementing a demand paging jitter buffer algorithm An apparatus for providing storage is provided that includes a jitter buffer element. The jitter buffer element includes a primary jitter buffer storage that includes a primary low water mark and a primary high water mark. The jitter buffer element also includes a s... | 05/06/2008 |
| 7366804 | Programmatic time-gap defect correction apparatus and method A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corre... | 04/29/2008 |
| 7366803 | Integrated circuit for buffering data by removing idle blocks to create a modified data stream when memory device is not near empty A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of co... | 04/29/2008 |
| 7365796 | System and method for video signal decoding using digital signal processing A digital signal processing based decoder is disclosed. The decoder asynchronously samples video signals. By doing so, the decoder can work in pseudo real-time and without analog interface components improving performance while reducing cost. ... | 04/29/2008 |
| 7366801 | Method for buffering work requests Disclosed is a technique for buffering work requests. It is determined that a work request is about to be placed into an in-memory structure. When the in-memory structure is not capable of storing the work request, a work request ordering identifier for the work req... | 04/29/2008 |
| 7362771 | Reduced latency FIFO A First-In-First-Out (FIFO) block to buffer a packet having a size is presented. The FIFO block includes a receiver to receive a data frame including the packet and overhead information, and to extract the packet from the data frame. A buffer has a plurality of memo... | 04/22/2008 |
| 7363400 | Data transfer switch When the capacity availability of buffer memory provided to an output port of a frame to be transferred is exceeding a predetermined value, a crossbar switch is used for path change of the frame. When the capacity availability of the buffer memory of the output port... | 04/22/2008 |
| 7363395 | Intermediate device capable of communicating using different communication protocols A method according to one embodiment may include determining, at least in part, by an intermediate device at least one communication protocol via which at least one storage device connected to the intermediate device is capable of communicating. In this embodiment, ... | 04/22/2008 |
| 7363412 | Interrupting a microprocessor after a data transmission is complete A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives ... | 04/22/2008 |
| 7360026 | Method and apparatus for synchronizing data with a reduced clock cycle response time A data buffering unit includes a memory that stores data from a data transmitting device. The data buffering unit also includes a memory read manager that prepares data stored in the memory for output prior to receiving a request for the data from a data reading dev... | 04/15/2008 |
| 7359618 | Information recording/reproducing apparatus and information recording/reproducing method An information recording/playback apparatus capable of recording and playing back data on and from a magnetic tape through a network. A monitoring unit 15 regularly monitors the state of the data stored in a temporary storage unit 14. A first controlli... | 04/15/2008 |
| 7359376 | Serial compressed bus interface having a reduced pin count There is provided a serial compressed bus interface having a reduced pin count. The interface includes a serial-to-parallel converter having a single serial data input line adapted to receive time-division multiplexed serial data from a plurality of data sources. En... | 04/15/2008 |
| 7356624 | Interface between different clock rate components A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer | 04/08/2008 |
| 7356648 | Shared buffer having hardware controlled buffer regions Buffer memories having hardware controlled buffer space regions in which the hardware controls the dimensions of the various buffer space regions to meet the demands of a particular system. The hardware monitors the usage of the buffer data regions over time and sub... | 04/08/2008 |
| 7353298 | Data transfer processing method Processing which, in conventional data transfer processing, entails the use of the common bus when performing (1) processing to confirm the interrupt state, performed via the common bus employing an interrupt register and interrupt mask register, and (2) confirmatio... | 04/01/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7350066 | Computer peripheral operating event responding method and system A computer peripheral operating event responding method and system is proposed, which is designed for use in conjunction with a computer platform for providing a peripheral operating events responding function, and which is more advantageous to use than prior art pa... | 03/25/2008 |
| 7349675 | Low latency data stream encoding and transmission Described is a communication system including mobile communication devices. In the described system, the mobile devices may be wrist-worn watches such as are in common use today, except that the watches are specially configured to receive data in a “broadcast” m... | 03/25/2008 |
