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| Number | Title | Issue Date |
| 7865637 | System of hardware objects Elements of the inventive development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the description defines the topolo... | 01/04/2011 |
| 7805552 | Partial packet write and write data filtering in a multi-queue first-in first-out memory system A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packe... | 09/28/2010 |
| 7774522 | Cache stashing processor control messages A system and method have been provided for pushing cacheable control messages to a processor. The method accepts a first control message, identified as cacheable and addressed to a processor, from a peripheral device. The first control message is allocated into a ca... | 08/10/2010 |
| 7426604 | Virtual output buffer architecture A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination ... | 09/16/2008 |
| 7412546 | System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buff... | 08/12/2008 |
| 7401169 | Counter updating system using an update mechanism and different counter utilization mechanism Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms for maintaining counters, such as in, but not limited to a packet switching system, and updating a secondary counter storage based on values of the counters and e... | 07/15/2008 |
| RE40317 | System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the ... | 05/13/2008 |
| 7370133 | Storage controller and methods for using the same In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later ... | 05/06/2008 |
| 7356624 | Interface between different clock rate components A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer | 04/08/2008 |
| 7337247 | Buffer and method of diagnosing buffer failure A buffer includes an input unit that inputs data; an output unit that outputs the data; a plurality of registers that stores the data while sequentially shifting the data from the input unit to the output unit; an output-data selecting unit that selects desired data... | 02/26/2008 |
| 7334063 | Method and device for register access according to identifier register A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the regist... | 02/19/2008 |
| 7334091 | Queue memory management The present disclosure includes systems and techniques relating to FIFO queue memory. In general, in one implementation, a queue memory receives and stores information and supports first-in-first-out read and out-of-order read operations with information shifting wi... | 02/19/2008 |
| 7330911 | Accessing a memory using a plurality of transfers A method of operating a circuit, comprising the steps of (A) buffering a read signal received within a plurality of first transfers to the circuit, (B) transmitting the read signal in a second transfer from the circuit, (C) buffering a first write signal received in... | 02/12/2008 |
| 7313104 | Wireless computer system with latency masking A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the ... | 12/25/2007 |
| 7302614 | Bus analyzer capable of managing device information A bus analyzer for tracing data flow on a bus which connects a host computer to peripheral devices, comprises an initialization information memory in which device information transferred by the peripheral device to the host computer at an initialization of connectin... | 11/27/2007 |
| 7302503 | Memory access engine having multi-level command structure A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer fi... | 11/27/2007 |
| 7296101 | Method and system for using a patch module to process non-posted request cycles and to control completions returned to requesting device A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system includes a patch module coupled to a completion queue included in the I/O... | 11/13/2007 |
| 7281071 | Method for designing an initiator in an integrated circuit A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring wh... | 10/09/2007 |
| 7260658 | Verifying input/output command data by separately sending data to be written and information about contents of the data Techniques for verifying input/output (I/O) command data are provided. Information about the contents of the data are specified in the I/O command. After an application issues the I/O command, a subsequent component, such as a controller, uses the information to ver... | 08/21/2007 |
| 7254655 | Software and process for low-latency audio recording A process and software for aggressive capture of digital recording on computers, for the purpose of reducing audio latency, which includes periodic frequent polling of a recording buffer containing audio recording data and a known value, reading out data values that... | 08/07/2007 |
| 7251735 | Buffer overflow protection and prevention A method and apparatus for protecting against a buffer over flow attack. In one variation, an executable software program is divided into an executable image, a data image, and an execution history image. The operating system processes an executable statement in the... | 07/31/2007 |
| 7251815 | Multiple virtual machines sharing processor and work queue in memory having program/dispatch functions for assigning and accessing work items while the virtual machine was not idle A system, computer program product and method for dispatching work items in a virtual machine operating system. The virtual machine operating system defines first and second virtual machines. First and second work queues are created in a memory. The first virtual ma... | 07/31/2007 |
| 7249206 | Dynamic memory allocation between inbound and outbound buffers in a protocol handler An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer... | 07/24/2007 |
| 7246182 | Non-blocking concurrent queues with direct node access by threads Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue... | 07/17/2007 |
| 7239645 | Method and apparatus for managing payload buffer segments in a networking device A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the d... | 07/03/2007 |
| 7231469 | Disk controller A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the ... | 06/12/2007 |
| 7218468 | Writing synchronized data to magnetic tape Synchronized data is written to magnetic tape while reducing the number of backhitches. A controller detects a pattern of synchronizing events for received data records to be written to tape; writes each transaction of data records to the magnetic; tape; accumulates... | 05/15/2007 |
| 7216185 | Buffering apparatus and buffering method Buffer control means and output control means are included within a buffering apparatus. Data longer than the width of data bus is read by single access from buffer means. Rather than signal line control for each bus width, signal line control for each data group is... | 05/08/2007 |
| 7213138 | Data transmission apparatus, system and method, and image processing apparatus A data transmission system where an image providing device and a printer are directly connected by a 1394 serial bus, a command is sent from the image providing device to the printer, then a response to the command is returned from the printer to the image providing... | 05/01/2007 |
| 7200696 | System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each da... | 04/03/2007 |
| 7197582 | Low latency FIFO circuit for mixed clock systems A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordanc... | 03/27/2007 |
| 7185029 | Method and apparatus for maintaining, and updating in-memory copies of the first and second pointers to reference the new versions of the first and second control structures that indicate available and allocated portions of usable space in the data file Method and apparatus for expanding usable space for an application data file. A control file is maintained with control structures that indicate available and allocated portions of usable space in the data file, along with quantities of available space in portions o... | 02/27/2007 |
| 7174443 | Run-time reconfiguration method for programmable units A method of run-time reconfiguration of a programmable unit is provided, the programmable unit including a plurality of reconfigurable function cells in a multidimensional arrangement. An event is detected. The source of the detected event is determined, and an addr... | 02/06/2007 |
| 7167934 | Peripheral device data transfer protocol A client driver requests data packet transfers from a peripheral device through a protocol stack and a host controller. The protocol stack receives the data transfer request and allocates the request into the host controller schedule. The host controller schedule re... | 01/23/2007 |
| 7145566 | Systems and methods for updating a frame buffer based on arbitrary graphics calls A method for dividing a display into zones at system initialization for tracking which zones have any pixels revised so that, when the time comes to update the display, only the zones requiring revision (that is, those zones in which any pixel has been revised) are ... | 12/05/2006 |
| 7136938 | Command ordering based on dependencies A method, apparatus, system, and signal-bearing medium that in various embodiments determine whether to execute a command in a queue or whether to wait until another command or commands completed. The determination is based on a combination of an in-use vector and a... | 11/14/2006 |
| 7124286 | Establishing an operating mode in a processor A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size w... | 10/17/2006 |
| 7080170 | Circular buffer using age vectors An apparatus comprises a buffer comprising a plurality of entries, a plurality of age vectors, and a control circuit coupled to the buffer. Each of the age vectors corresponds to one or more of the entries. Responsive to data being provided to the buffer to be writt... | 07/18/2006 |
| 7076545 | Load balancing the servicing of received packets A system and method for distributing a portion of the processing of a received packet among a plurality of service threads. When an ISR or similar process retrieves a packet from a communication interface via a receive descriptor ring, it places the packet on one of... | 07/11/2006 |
| 7072998 | Method and system for optimized FIFO full conduction control Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and th... | 07/04/2006 |
