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| Number | Title | Issue Date |
| 8055819 | Information processor An information processor (program processing unit 1) for managing a data sequence in a fixed order comprises a direction array (reference data storage section 2) for storing a reference to each data item of the data sequence in an element of the index ... | 11/08/2011 |
| 8055818 | Low latency queue pairs for I/O adapters A low-latency queue pair (QP) is provided for I/O Adapters that eliminates the overhead associated with work queue elements (WQEs) and defines the mechanisms necessary to allow the placement of the message directly on the queue pair. ... | 11/08/2011 |
| 7979608 | Lane to lane deskewing via non-data symbol processing for a serial point to point link Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the n... | 07/12/2011 |
| 7934027 | Critical resource management In one embodiment, a method of managing critical resource usage in a storage network comprises receiving, in a storage controller, an input/output operation from a host, wherein the input/output operation identifies a storage unit, placing the input/output operation... | 04/26/2011 |
| 7913001 | Lane to lane deskewing via non-data symbol processing for a serial point to point link Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the n... | 03/22/2011 |
| 7904618 | Buffer managing method and buffer managing apparatus A buffer is provided with a leading pointer and a following pointer. A bitmap in which two bits are assigned to each block is updated to retain which states blocks are in, busy, write-completed, or read-completed. Under the constraint that the two pointers move in t... | 03/08/2011 |
| 7831749 | Including descriptor queue empty events in completion events Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the ho... | 11/09/2010 |
| 7802033 | Adaptive bandwidth distribution system for high-performance input/output devices with variable throughput A method for issuing shadow requests to manage bandwidth allocation between an application that issues input/output (I/O) operation requests and an I/O device. A bandwidth manager detects the completion of an I/O operation, which includes either a read operation or ... | 09/21/2010 |
| 7783797 | Adaptive bandwidth distribution system for high-performance input/output devices with variable throughput A method for issuing shadow requests to manage bandwidth allocation between an application that issues input/output (I/O) operation requests and an I/O device. A bandwidth manager detects the completion of an I/O operation, which includes either a read operation or ... | 08/24/2010 |
| 7774521 | Method and apparatus for reducing power consumption for isochronous data transfers A method and article for reducing power consumption for isochronous data transfers are described. The method may include receiving packets of data having multimedia information with empty spaces. The packets of data may be stored in a first buffer having a first buf... | 08/10/2010 |
| 7743185 | Method, system, and computer program product for dynamically selecting software buffers for aggregation according to current system characteristics A method, system, and computer program product in a data processing system are disclosed for dynamically selecting software buffers for aggregation in order to optimize system performance. Data to be transferred to a device is received. The data is stored in a chain... | 06/22/2010 |
| 7647438 | Binary base address sorting method and device with shift vector A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array o... | 01/12/2010 |
| 7644206 | Command queue ordering by positionally pushing access commands A data storage system is provided with command queue controller circuitry for positionally pushing pending access commands from a command queue to a selected target zone of a storage space. A method is provided for dividing a storage space into a plurality of LBA zo... | 01/05/2010 |
| 7603497 | Method and apparatus to launch write queue read data in a microprocessor recovery unit A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction co... | 10/13/2009 |
| 7526583 | Method and apparatus to launch write queue read data in a microprocessor recovery unit A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction co... | 04/28/2009 |
| 7493428 | Method and system for dynamic queue splitting for maximizing throughput of queue based operations while maintaining per-destination order of operations A system for providing dynamic queue splitting to maximize throughput of queue entry processing while maintaining the order of queued operations on a per-destination basis. Multiple queues are dynamically created by splitting heavily loaded queues in two. As queues ... | 02/17/2009 |
| 7490180 | Method, system, and computer program product for dynamically selecting software buffers for aggregation according to current system characteristics A method, system, and computer program product in a data processing system are disclosed for dynamically selecting software butters for aggregation in order to optimize system performance. Data to be transferred to a device is received. The data is stored in a chain... | 02/10/2009 |
| 7457893 | Method for dynamically selecting software buffers for aggregation according to current system characteristics A method is disclosed for dynamically selecting software buffers for aggregation in order to optimize system performance. Data to be transferred to a device is received. The data is stored in a chain of software buffers. Current characteristics of the system are det... | 11/25/2008 |
| 7426604 | Virtual output buffer architecture A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination ... | 09/16/2008 |
| 7412546 | System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buff... | 08/12/2008 |
| 7404058 | Method and apparatus for avoiding collisions during packet enqueue and dequeue A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or stat... | 07/22/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370054 | Method and apparatus for indexing a hash table which is organized as a linked list One embodiment of the present invention provides a system that implements a hash table that is fully dynamic and lock-free. During a lookup in the hash table the system first uses a hash key to lookup a bucket pointer in a bucket array. Next, the system follows the ... | 05/06/2008 |
| 7370116 | Approach to minimize worst-case queuing delay for a switching communication system with transmission constraints An approach for minimizing queuing delay of packets is disclosed. M number of queues are configured to store packets. A memory stores a search order table that has table entries corresponding to the M queues. Specifically, the table entries store values that corresp... | 05/06/2008 |
| 7366831 | Lock-free bounded FIFO queue mechanism A system includes a processor and a size bounded first-in first-out (FIFO) memory that is connected to the processor and a display is connected to the processor. A managing process to run on the processor to manage the FIFO memory structure. The FIFO memory includes... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366803 | Integrated circuit for buffering data by removing idle blocks to create a modified data stream when memory device is not near empty A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of co... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7362749 | Queuing closed loop congestion mechanism An exemplary queuing congestion mechanism and method are disclosed that provide congestion management at an egress port of a packet switch. The queuing congestion mechanism includes at least a first, a second and a third queue, which each have an input, an output, a... | 04/22/2008 |
| 7360041 | Method for priority scheduling and priority dispatching of store conditional operations in a store queue A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an addit... | 04/15/2008 |
| 7356624 | Interface between different clock rate components A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer | 04/08/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7346715 | Data communication control device with peripheral device Loss of data to be transmitted from a peripheral device to a host before a software hierarchy of the host side completely starts is prevented. In a time period before a host completely reached a normal operation mode from a sleep mode, data outputted from a receiver... | 03/18/2008 |
| 7336682 | Network architecture and methods for transparent on-line cross-sessional encoding and transport of network communications data A computer implemented method and system for transferring data packets includes intercepting a stream of data packets at the connectionless network layer from a client or server, encoding and encapsulating the data packets, transmitting the encoded data packets, dec... | 02/26/2008 |
| 7337244 | Data transfer apparatus, storage device control apparatus and control method using storage device control apparatus A data transfer apparatus includes a memory having first and second queues for storing data transfer information that includes information specifying a first memory area and information specifying a second memory area, a first processor which registers the data tran... | 02/26/2008 |
| 7333502 | Services processor having a queue operations unit and an output scheduler In a services processor, a queue operations unit controls the output of processed data packets from the services processor. In accordance with a hybrid list/calendar queue priority scheme, the queue operations unit uses a unique data structure comprising a tree of c... | 02/19/2008 |
| 7330917 | Decimation of fixed length queues having a number of position for holding data wherein new data is favored over old data Decimation of data from a fixed length queue retaining a representative sample of the old data. Exponential decimation removes every nth sample. Dithered exponential decimation offsets the exponential decimation approach by a probabilistic amount. Recursive decimati... | 02/12/2008 |
| 7321985 | Method for achieving higher availability of computer PCI adapters Higher availability in a computer system is achieved by utilizing PCI (Peripheral Component Interconnect) adapters capable of dynamically switching between being controlled by a system processor and a specialized input/output processor (IOP). A method of fault recov... | 01/22/2008 |
| 7313578 | Method and apparatus for cascading data through redundant data storage units A data storage facility for transferring data from a data altering apparatus, such as a production data processing site to a remote data receiving site. The data storage facility includes a first data store for recording each change in the data generated by the data... | 12/25/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
