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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 8127058 | System and method of video decoding using hybrid buffer In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in fir... | 02/28/2012 |
| 8082374 | Information processing apparatus, information processing system, method of processing information, and computer program An information processing apparatus includes a communication processing unit configured to communicate with an external communication device; and a data processing unit configured to communicate with the communication processing unit and carry out data processing. T... | 12/20/2011 |
| 8065450 | Frame transfer method and device In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffe... | 11/22/2011 |
| 8032674 | System and method for controlling buffer memory overflow and underflow conditions in storage controllers A method for maintaining flow control in a buffer memory coupled to a storage controller is provided. The storage controller includes, first and second counters that are used to monitor when data is read from a buffer memory and when data is transferred from the buf... | 10/04/2011 |
| 7984212 | System and method for utilizing first-in-first-out (FIFO) resources for handling differences in data rates between peripherals via a merge module that merges FIFO channels A system and method for sharing peripheral first-in-first-out (FIFO) resources is disclosed. In one embodiment, a system for utilizing peripheral FIFO resources includes a processor, a first peripheral FIFO controller and a second peripheral FIFO controller coupled ... | 07/19/2011 |
| 7899811 | Boosting throughput of a computer file server A software layer for boosting the throughput of a computer file server by reducing the number of required mechanical accesses to the physical storage is provided. The throughput boost is achieved through the combination of extending the data requests along the file ... | 03/01/2011 |
| 7886090 | Method for managing under-runs and a device having under-run management capabilities A method for managing under-runs and a device having under-run management capabilities. The method includes retrieving packets from multiple buffers, monitoring a state of a multiple buffers, determining whether an under-run associated with a transmission attempt of... | 02/08/2011 |
| 7865636 | Buffer management for wireless USB isochronous in endpoints An apparatus such as a Device Wire Adapter (DWA) with improved buffer management and packaging of Wireless Universal Serial Bus (WUSB) isochronous packets for transmission to a host. The apparatus includes an isochronous IN endpoint that receives data segments from ... | 01/04/2011 |
| 7836230 | Managing multiple host requests in queued commands that corresponds to receipt of stored acknowledgement commands from the host Management of requests from a host to an external storage medium. An execution queue stores commands to be executed, and each command corresponds to a request from the host for data. A holding queue stores executed commands until receipt of an acknowledgment from th... | 11/16/2010 |
| 7730239 | Data buffer management in a resource limited environment An apparatus and method is provided to facilitate Input/Output (I/O) transfer in resource limited storage environment. Scatter gather list, segment and memory data buffer allocation are dynamically managed. I/O transfer performance is increased through the use of a ... | 06/01/2010 |
| 7725625 | Latency insensitive FIFO signaling protocol Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in... | 05/25/2010 |
| 7519747 | Variable latency buffer and method of operation A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or incre... | 04/14/2009 |
| 7437487 | Storage medium array controller, a storage medium array apparatus, a storage medium drive, a method of controlling a storage medium array, and a signal-bearing medium embodying a program of a storage medium array controller A storage medium drive is controllable by a storage medium array controller. the storage medium array controller receives a data storage medium drive information and the storage medium array controller sets a data transmission parameter with respect to the storage m... | 10/14/2008 |
| 7430623 | System and method for buffering data received from a network A system for buffering data received from a network comprises a network socket, a plurality of buffers, a buffer pointer pool, receive logic, and packet delivery logic. The buffer pointer pool has a plurality of entries respectively pointing to the buffers. The rece... | 09/30/2008 |
| 7425961 | Display panel driver unit To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port RAM without reduction in an operation speed. A reservation buf... | 09/16/2008 |
| 7426604 | Virtual output buffer architecture A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination ... | 09/16/2008 |
| 7412546 | System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buff... | 08/12/2008 |
| 7409475 | System and method for a high-speed shift-type buffer Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. O... | 08/05/2008 |
| 7380029 | Disk driver cluster management of time shift buffer A file allocation system for a hard disk drive includes a memory with driver logic and a processor configured with the driver logic to receive a request to allocate hard disk space of a defined size for a buffer file. In some embodiments, the processor is configured... | 05/27/2008 |
| 7366804 | Programmatic time-gap defect correction apparatus and method A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corre... | 04/29/2008 |
| 7360040 | Interleaver for iterative decoder Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implem... | 04/15/2008 |
| 7359996 | Data transfer control device, electronic equipment, and data transfer control method Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferre... | 04/15/2008 |
| 7359997 | USB data transfer control device including first and second USB device wherein destination information about second device is sent by first device A transfer controller (or a host controller) issues IN tokens to a plurality of USB devices connected to USB and including first and second USB devices. When data including destination information which specifies the second USB device as a destination has been recei... | 04/15/2008 |
| 7356030 | Network switch cross point A switching fabric having cross points that process multiple stripes of serial data. Each cross point includes a plurality of port slices and ports. Each port includes a plurality of FIFOs, a FIFO read arbitrator, a multiplexer, a dispatcher, and an accumulator. In ... | 04/08/2008 |
| 7356625 | Moving, resizing, and memory management for producer-consumer queues by consuming and storing any queue entries from an old queue before entries from a new queue Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer,... | 04/08/2008 |
| 7356631 | Apparatus and method for scheduling requests to source device in a memory access system An apparatus and method for scheduling requests to a source device is provided. The apparatus comprises a high-priority request queue for storing a plurality of high-priority requests to the source device; a low-priority request queue for storing a low-priority requ... | 04/08/2008 |
| 7356624 | Interface between different clock rate components A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer | 04/08/2008 |
| 7353303 | Time slot memory management in a switch having back end memories stored equal-size frame portions in stripes A switch comprising front-end and back-end application specific integrated circuits (ASICs) is disclosed. Frame storage and retrieval in the switch is achieved by dividing a frame into equal sized portions that are sequentially stored in switch memory during an assi... | 04/01/2008 |
| 7350889 | Printer with loudspeaker interface A printer includes a loudspeaker that announces error messages and the like. The error messages are stored as sound files in an onboard memory device. A central processor communicates with a speaker interface circuit by means of a data bus. A DMA controller is provi... | 04/01/2008 |
| 7346715 | Data communication control device with peripheral device Loss of data to be transmitted from a peripheral device to a host before a software hierarchy of the host side completely starts is prevented. In a time period before a host completely reached a normal operation mode from a sleep mode, data outputted from a receiver... | 03/18/2008 |
| 7340541 | Method of buffering bidirectional digital I/O lines A system and method for buffering bidirectional digital input/output (I/O) lines. The system (e.g., data acquisition system) may comprise a device including circuitry for buffering bidirectional digital lines. A first integrated circuit (IC) of the device includes a... | 03/04/2008 |
| 7337260 | Bus system and information processing system including bus system In a bus connection circuit for connecting buses having different bit widths, number of clock cycles can be reduced, and hardware amount can be reduced. The bus connection circuit connects buses of mutually different bit widths having control lines and data lines co... | 02/26/2008 |
| 7337248 | Adaptive synchronization method for communication in storage systems A method for transferring data in a storage system is provided. The method includes setting a catch-up threshold for accepting data requests from a port where the queue value corresponds to a number of requests collected from an input queue for every CPU interrupt, ... | 02/26/2008 |
| 7333581 | Method of processing data for a decoding operation using windows of data The present invention relates to a method using windows of data, a window (w) comprising data to be written and to be read and having a size. It is characterized in that it comprises:* A step of writing a current window of data into a unique buffer (BUF) in a first ... | 02/19/2008 |
| 7334063 | Method and device for register access according to identifier register A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the regist... | 02/19/2008 |
| 7330900 | Low-latency packet processor Packets of real-time media streams are processed at a network node such within a desired maximum latency less than the frame interval of the streams. The media streams have respective packet rates all substantially equal to a nominal packet rate and respective packe... | 02/12/2008 |
| 7320039 | Method for processing consistent data sets The invention relates to a method for processing consistent data sets by asynchronous application of a subscriber in an isochronous, cyclical communication system. According to the invention, by connecting a communication memory and a consistency, transmission and r... | 01/15/2008 |
| 7319860 | Pseudo-interactive input processing in wireless environments An electronic communications device including a user input device for inputting characters; and buffering and communications systems for storing in a buffer characters input by the user input device, and transmitting the content of the buffer over a communications l... | 01/15/2008 |
| 7320042 | Dynamic network interface A dynamic network interface is described, intended to enable the efficient processing of received data within a computer network by a target computer system by reducing excessive copying of the received data prior to being accessed by a network software application.... | 01/15/2008 |
| 7313638 | Command accumulation tool A command accumulation tool, a testing tool for a queue, and a method, are provided, which, for example, may cause commands to accumulate in queue(s). In one embodiment, a testing tool comprises an I/O interface for connecting with a target having the queue(s); and ... | 12/25/2007 |
