Bizarre Patents
A haircutting appliance comprises an enclosed housing having a hollow handle connecting the housing to a vacuum source to carry away cut hairs from a subject's head.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8190794 | Control function for memory based buffers Instantiating a plurality of buffers in a random access memory by storing in the random access memory (RAM) a plurality of descriptors each containing a base address, at least one address pointer and a size to define a corresponding one of the plurality of buffers. ... | 05/29/2012 |
| 8185674 | System having a plurality of buffers for providing audio for synchronized playback to multiple audio devices An audio system communicates with an aggregate device that includes multiple audio devices. When providing audio data for playback, the system compensates for presentation latency differences between the various audio devices. In addition, the system adjusts for dev... | 05/22/2012 |
| 8176223 | System and method for storing communications intended for different groups using a limited amount of space A system and method stores wirelessly received communications for wireless retransmission, making space in a storage device, if necessary, by deleting any one or more communications corresponding to the same group as the received communication. If storage in the sto... | 05/08/2012 |
| 8171188 | Method of handling successive bitstream extraction and packing and related device To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equ... | 05/01/2012 |
| 8166214 | Shared storage for multi-threaded ordered queues in an interconnect In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries t... | 04/24/2012 |
| 8166213 | Controller with indirect accessible memory A controller has an interface, a buffer memory, a first set of registers for accessing the buffer memory, a second set of registers independent from the first set of registers for accessing the buffer memory, and a control unit for decoding and executing buffer memo... | 04/24/2012 |
| 8156264 | Digital output sensor FIFO buffer with single port memory A digital output sensor includes a sensor module for providing digital data representative of a sensed parameter, a First-In-First-Out (FIFO) memory having a single port memory, and an output port for transmitting the digital data. The digital data from the sensor m... | 04/10/2012 |
| 8156265 | Data processor coupled to a sequencer circuit that provides efficient scalable queuing and method A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit,... | 04/10/2012 |
| 8151019 | Adaptive network traffic shaper A network traffic shaper adjusts the rate of data flowing from a packet source to a packet sink responsive to priority assigned to the packets pursuant to their ability to match a series of filters. Each packet is applied to a queue depending on its classification. ... | 04/03/2012 |
| 8135885 | Data packer for packing and aligning write data A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower ba... | 03/13/2012 |
| 8135886 | Instruction set for programmable queuing A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such in... | 03/13/2012 |
| 8131895 | Interrupt management for multiple event queues Method of managing interaction between a host subsystem and a peripheral device. Roughly described, the peripheral device writes an event into an individual event queue, and in conjunction therewith, also writes a wakeup event into an intermediary event queue. The w... | 03/06/2012 |
| 8131893 | Memory device that mediates mutual communication among a pluraliity of CPUs In a memory device, data can be transmitted from a first CPU to a second CPU via an individual register or a shared SRAM, for example. The data transmitted from the first CPU to the second CPU via the individual register also passes through a FIFO. When first data i... | 03/06/2012 |
| 8131894 | Method and system for a sharing buffer A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource m... | 03/06/2012 |
| 8127056 | Data transfer control device including a switch circuit that switches write destination of received packets A data transfer control device including: a link controller which analyzes a packet received through a serial bus; a packet detection circuit which detects completion or start of packet reception based on analysis result of the received packet; first and second pack... | 02/28/2012 |
| 8127057 | Multi-level buffering of transactional data An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory acces... | 02/28/2012 |
| 8122169 | Data buffering based on priority tagging of input data A data buffer device includes: a tag value generation circuit that generates a tag value; a first buffer that stores first priority data; a second buffer that stores second priority data; and a data output circuit that outputs the first priority data or the second p... | 02/21/2012 |
| 8122168 | Method for implementing concurrent producer-consumer buffers A method and a system for implementing concurrent producer-consumer buffers are provided. The method and system in one aspect uses separate locks, one for putter and another for taker threads operating on a concurrent producer-consumer buffer. The locks operate inde... | 02/21/2012 |
| 8108574 | Apparatus and methods for translation of data formats between multiple interface types Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consu... | 01/31/2012 |
| 8099533 | Controller and a method for controlling the communication between a processor and external peripheral device The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling t... | 01/17/2012 |
| 8090883 | Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise st... | 01/03/2012 |
| 8086769 | Method for detecting circular buffer overrun A computer implemented method, data processing system, and computer program product for detecting circular buffer overflow. When an entry in the circular buffer is read, a valid mark bit in the entry is set to an inactive state and the location of the entry is store... | 12/27/2011 |
| 8078772 | Digital phase relationship lock loop In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second ... | 12/13/2011 |
| 8073995 | Efficient low-latency buffer An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional buffer in an audio playback device to buffer both output and input data. The audio buffer includes two modes of operation. The fi... | 12/06/2011 |
| 8073994 | Data transfer, synchronising applications, and low latency networks Asynchronous network interface and method of synchronisation between two applications on different computers is provided. The network interface contains snooping hardware which can be programmed to contain triggering values comprising either addresses, address range... | 12/06/2011 |
| 8069284 | Semiconductor memory device, memory system and data recovery methods thereof A semiconductor memory device includes a nonvolatile memory device having a plurality of physical sectors, and a memory controller configured to translate a logical address received from a host to a physical address, with reference to mapping data that defines a cor... | 11/29/2011 |
| 8060669 | Memory controller with automatic command processing unit and memory system including the same Provided is a memory controller configured to control a flash memory device. The memory controller includes: a buffer memory configured to store data to be written in the flash memory device; a buffer memory interface configured to control read and write operations ... | 11/15/2011 |
| 8055817 | Efficient handling of queued-direct I/O requests and completions Computer program products and methods for efficient handling of queued-direct input/output (QDIO) requests and completions at an adapter in communication with an I/O device are provided. A method includes accessing a queue with one or more storage block address list... | 11/08/2011 |
| 8051226 | Circular buffer support in a single instruction multiple data (SIMD) data processor A method is provided for generating a control vector. The method comprising: providing a circular buffer having a plurality of storage elements that are arranged sequentially from a designated first storage element to a designated last storage element, and when the ... | 11/01/2011 |
| 8046507 | Computer, external storage and method for processing data information in external storage The present invention provides a computer, comprising: a processor for processing data; a system bus connected to the processor; a management unit connected to the system bus; and an external storage connected to the system bus through the management unit, wherein t... | 10/25/2011 |
| 8046506 | FIFO system and operating method thereof FIFO systems and operating method thereof are provided to transfer data between a first device and a second device. In the FIFO system, a memory controller serves as an interface to access a memory device for storage of the data, and a CPU processes instructions to ... | 10/25/2011 |
| 8041856 | Skip based control logic for first in first out buffer A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, ... | 10/18/2011 |
| 8037220 | Techniques for providing audio for synchronized playback by multiple devices An audio system communicates with an aggregate device that includes multiple audio devices. When providing audio data for playback, the system compensates for presentation latency differences between the various audio devices. In addition, the system adjusts for dev... | 10/11/2011 |
| 8032673 | Transaction ID filtering for buffered programmed input/output (PIO) write acknowledgements A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactons sources. Each PIO write operation may include a source identifier that identifies the ... | 10/04/2011 |
| 8032672 | Increased speed of processing of audio samples received over a serial communications link by use of channel map and steering table A method and apparatus for processing data samples utilizes a channel map populated by device descriptor, or by an application program interface. Packet processing code loops through all of the samples contained in a packet while incrementing through a channel map a... | 10/04/2011 |
| 8019921 | Intelligent memory buffer A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes... | 09/13/2011 |
| 8019202 | Content reproduction appratus, content reproduction method, and content reproduction system with varied-speed reproduction requests A content reproduction method is provided, which acquires, from a data transmission apparatus, first streaming data that is used to play a content at a first speed, and records the first streaming data on a storage medium. The content reproduction method plays the c... | 09/13/2011 |
| 8019920 | Method to improve operating performance of a computing device The system includes a microprocessor, a first buffer, a second buffer, and a control circuit. The control circuit includes a memory and an interface. The control circuit is configured to determine a first buffer value and compare the first buffer value to a predeter... | 09/13/2011 |
| 8015330 | Read control in a computer I/O interconnect In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether... | 09/06/2011 |
| 8015328 | Information storage device, information processing system, and setting method of data transfer mode of information processing device An information storage device includes a storage that stores transfer data from an information processing device, the information storage device being removably connected to the information processing device, a switch unit that switches a data transfer mode of the i... | 09/06/2011 |
