Bizarre Patents
An extension member is attachable to a trailer hitch and extends away from the vehicle and is connected to a seating frame supporting a toilet seat.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7882283 | Virtualization support in a multiprocessor storage area network Support for virtualization in a storage area networks may be provided using a variety of techniques. In one embodiment of the present invention, exchange level load balancing may be provided by determining if input/outputs (IOs) received by a device are new. If a pa... | 02/01/2011 |
| 7631117 | Method for communicating between host and storage device, storage device, host, and system comprising storage device and host Embodiments of the invention improve the efficiency of communication processing between a host and a storage device. In one embodiment, a data processing system includes a storage device and a host. The host gives the storage device an instruction to perform specifi... | 12/08/2009 |
| 7631116 | Method and system for packet encryption A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the pac... | 12/08/2009 |
| 7620751 | Command scheduling and affiliation management for serial attached storage devices According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided ... | 11/17/2009 |
| 7558888 | Enhanced access to hidden data storage An apparatus for executing user commands in digital equipment operating in a USB mass storage (UMS) mode is configured in such a manner that a USB connecting unit transmits and receives commands and data to and from a PC serving as a host through a universal serial ... | 07/07/2009 |
| 7349999 | Method, system, and program for managing data read operations on network controller with offloading functions Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target dat... | 03/25/2008 |
| 7302504 | Methods and apparatus for providing data transfer control A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work ind... | 11/27/2007 |
| 7281030 | Method of reading a remote memory In an example embodiment, a method of reading data from a remote device transfers data directly from the remote memory of the remote device to the local memory of the local device. A message is sent from the local device to the remote device which includes a transpo... | 10/09/2007 |
| 7243178 | Enable/disable claiming of a DMA request interrupt Machine-readable media, methods, and apparatus are described for performing direct memory access (DMA) transfers. In some embodiments, a device may generate an interrupt to request a DMA transfer. A DMA controller may claim the interrupt and may prevent a processor ... | 07/10/2007 |
| 7240350 | System and method for providing communications to processes A system and method provides communications to processes, handles transmissions of communications received from processes, and allows other manipulations of transmissions upon request by processes without an operating system call. ... | 07/03/2007 |
| 7213084 | System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmabl... | 05/01/2007 |
| 7188215 | Apparatus and method for renaming a cache line A microprocessor apparatus is provided that enables exclusive allocation and renaming a cache line. The apparatus includes translation logic and execution logic. The translation logic translates an allocate and rename instruction into a micro instruction sequence th... | 03/06/2007 |
| 7185125 | Device for transferring data via write or read pointers between two asynchronous subsystems having a buffer memory and plurality of shadow registers Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer register to the FIFO. Each pointer register is associated with a primary... | 02/27/2007 |
| 7111125 | Apparatus and method for renaming a data block within a cache A microprocessor apparatus is provided that enables exclusive allocation and renaming of a block of cache lines. The apparatus includes translation logic and execution logic. The translation logic translates a block allocate and rename instruction into a micro instr... | 09/19/2006 |
| 7038574 | Packet differentiation services A communication network comprising a routing system, a media gateway coupled to the routing system, and a network element coupled to the routing system. The media gateway, responsive to a status change of the media gateway, transfers a first packet for a location se... | 05/02/2006 |
| 7013305 | Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the duplexing of structures of the coupling facilities. Duplexing is performed on ... | 03/14/2006 |
| 6963934 | Hibernation of computer systems An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including c... | 11/08/2005 |
| 6959346 | Method and system for packet encryption A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list processes to perform on the packet... | 10/25/2005 |
| 6883037 | Fast data decoder that operates with reduced output buffer bounds checking Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on e... | 04/19/2005 |
| 6779060 | Multimodal user interface In a multi-modal user interface, user inputs may be made in various different ways. For instance, the user might use a keyboard, a speech system, a vision system, a mouse or pen. Different inputs made by the user may be related and may have different significance. A... | 08/17/2004 |
| 6748460 | Initiative passing in an I/O operation without the overhead of an interrupt Apparatus, method and program product for use in passing initiative to a processor for handling an I/O request for an I/O operation for sending data between a main storage and one or more devices. A hierarchy of vectors registers I/O requests by the devices to send ... | 06/08/2004 |
| 6697959 | Fault handling in a data processing system utilizing a fault vector pointer table A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an... | 02/24/2004 |
| 6665816 | Data shift register A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protoco... | 12/16/2003 |
| 6601122 | Exceptions and interrupts with dynamic priority and vector routing A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a po... | 07/29/2003 |
| 6401194 | Execution unit for processing a data stream independently and in parallel A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more comp... | 06/04/2002 |
| 6356970 | Interrupt request control module with a DSP interrupt vector generator In a system having an DSP, an ASIC and a memory, in which the ASIC generates a number of different competing interrupts for the DSP to service, the ASIC has an interrupt request control module which automatically provides the DSP with a vector pointing to... | 03/12/2002 |
| 6324600 | System for controlling movement of data in virtual environment using queued direct input/output device and utilizing finite state machine in main memory with two disjoint sets of states representing host and adapter states A method and an apparatus for controlling movement of data between any host and any network including a set of devices in a computing system environment having a main memory with a queuing mechanism having a plurality of queues capable of being shared bet... | 11/27/2001 |
| 6317803 | High-throughput interconnect having pipelined and non-pipelined bus transaction modes A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. T... | 11/13/2001 |
| 6134629 | Determining thresholds and wrap-around conditions in a first-in-first-out memory supporting a variety of read and write transaction sizes Data is read from a first-in-first-out (FIFO) queue. A first condition flag is generated which indicates whether a read transaction of a first transaction size may be performed. When a write address for the FIFO queue is greater than a read address for th... | 10/17/2000 |
| 6125410 | D.M.A. controller that determines whether the mode of operation as either interrupt or D.M.A. via single control line The invention discloses a communication system for exchanging data between a bus and at least one coupled data processing arrangement via a serial interface which is coupled to a microprocessor by a control line via a DMA unit. For effecting an efficient ... | 09/26/2000 |
| 6098144 | Solid state data processor with versatile multisource interrupt organization A data processor, includes a central processing unit, an interrupt handler for selectingly signalling a single interrupt vector to the central processing unit, and multiple interrupt sources that are daisy-chained to the interrupt handler, for therewith e... | 08/01/2000 |
| 6002877 | Interrupt control method for controlling an interrupt from a peripheral device to a processor A method for controlling an interrupt from a peripheral device to a processor, the peripheral device including at least an interrupt control unit, an interrupt request level holding unit, and an interrupt vector holding unit, which includes the steps of: ... | 12/14/1999 |
| 5948093 | Microprocessor including an interrupt polling unit configured to poll external devices for interrupts when said microprocessor is in a task switch state An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes an interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transac... | 09/07/1999 |
| 5925115 | Method and system for extending interrupt sources and implementing hardware based and software based prioritization of interrupts for an embedded processor The present invention comprises and interrupt controller for use with a programmable digital processor system. The interrupt controller of the present invention includes a plurality of interrupt blocks. The interrupt blocks are used for coupling to a corr... | 07/20/1999 |
| 5881294 | System for transforming PCI level interrupts A system for transforming computer system interrupts from state based interrupts to event based interrupts. The system of the present invention includes an interrupt acknowledge detection circuit adapted to detect an interrupt acknowledge from a computer ... | 03/09/1999 |
| 5850555 | System and method for validating interrupts before presentation to a CPU A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity c... | 12/15/1998 |
| 5790837 | Method and system for device virtualization based on an interrupt request in a dos-based environment A technique for providing device virtualization in an MS-DOS based operating environment, using an interrupt request (e.g., a non-maskable interrupt), is described. The technique includes executing an application on a processor within the MS-DOS based ope... | 08/04/1998 |
| 5761534 | System for arbitrating packetized data from the network to the peripheral resources and prioritizing the dispatching of packets onto the network A client interface supporting a plurality of peripheral channels and a network channel. The peripheral channels include a maintenance channel, message input channel, message output channel, express channel and several DMA channels. The client interface ro... | 06/02/1998 |
| 5734911 | Method of linking peripheral devices all of which use the same IRQ to a single interrupt procedure A method of linking peripheral devices to a single interrupt procedure in a computer is comprised of storing in an interrupt vector table of a BIOS ROM, a first pointer to an interrupt service routine related to one of a group of peripheral devices which ... | 03/31/1998 |
| 5659760 | Microprocessor having interrupt vector generation unit and vector fetching command unit to initiate interrupt processing prior to returning interrupt acknowledge information A microprocessor for performing an interrupt operation receives an interrupt-enable signal representative of occurrence of at least interrupt request and interrupt level information representative of a selected one of interrupt sources issuing the interru... | 08/19/1997 |
