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| Number | Title | Issue Date |
| 7765342 | Systems, methods, and computer program products for packing instructions into register files Embodiments of the present invention may provide for architectural and compiler approaches to optimizing processors by packing instructions into instruction register files. The approaches may include providing at least one instruction register file, identifying a pl... | 07/27/2010 |
| 7584310 | Signal processing device A signal processing device includes a start time obtaining part that obtains a start time when a predetermined process is started in response to an interrupt request associated with a valid edge of a pulse input signal, an edge occurrence time obtaining part that ob... | 09/01/2009 |
| 7426728 | Reducing latency, when accessing task priority levels One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt ... | 09/16/2008 |
| 7340547 | Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an ... | 03/04/2008 |
| 7330999 | Network storage appliance with integrated redundant servers and storage controllers A network storage appliance integrates a plurality of servers and a plurality of storage controllers into a single chassis. The storage controllers control transfers of data between the servers and storage devices controlled by the storage controllers. The servers a... | 02/12/2008 |
| 7302511 | Chipset support for managing hardware interrupts in a virtual machine system In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a dist... | 11/27/2007 |
| 7296097 | Memory card and initialization setting method thereof to avoid initializing operation failure in a memory card Whether an initial command outputted from a host is ‘CMD1’ or ‘CMD55+CMD41’ is detected with an initial command detection portion 8, and the result of detection is set in an SD/MMC register 13. Reset process for hardware an... | 11/13/2007 |
| 7287103 | Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less l... | 10/23/2007 |
| 7266630 | CPU contained LSI In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the common bus is not prevented in the CPU contained LSI. A CPU containe... | 09/04/2007 |
| 7234015 | PCIXCAP pin input sharing configuration for additional use as PCI hot plug interface pin input A method is provided for selectively using a PCIXCAP pin input to detect PCI/PCI-X bus mode or as DC pin input. The method provides a PCI/PCI-X device having PCIXCAP pin input, and a circuit having a plurality of voltage level detection structures and an output corr... | 06/19/2007 |
| 7188203 | Method and apparatus for dynamic suppression of spurious interrupts An apparatus and method for dynamic suppression of spurious interrupts in a computer system. More specifically, there is provided a method that comprises providing a look-up table comprising source IDs and corresponding time delays for each of a plurality of interru... | 03/06/2007 |
| 7185183 | Atomic update of CPO state A group of bit set and bit clear instructions are provided for a microprocessor to allow atomic modification of privileged architecture control registers. The bit set and bit clear instructions include an opcode that designates to the microprocessor that the instruc... | 02/27/2007 |
| 7185262 | Method and device for monitoring a data processing and transmission Data processing and transmission is monitored in a data processing unit. The data processing unit has a plurality of software modules, between which data is exchanged, a check sum is allocated to the data of a data transmission, which, in selected software modules i... | 02/27/2007 |
| 7149778 | Unsolicited electronic mail reduction The present invention involves reducing the amount of unsolicited e-mail. In one embodiment, a method for automatically detecting unsolicited electronic mail from a mailer and automatically notifying facilitators of the mailer of the unsolicited electronic mail is d... | 12/12/2006 |
| 7138989 | Display capable of displaying images in response to signals of a plurality of signal formats A display is capable of displaying images in response to signals of a plurality of signal formats. The display includes a controller that is coupled to a plurality of image data interfaces. When the plurality of image data interfaces are simultaneously operating, th... | 11/21/2006 |
| 7133926 | Broadcast compressed firmware flashing The described invention is directed to a system and related method for updating software in multiple remote communication devices where those communication devices are accessible only by relatively low bandwidth communication buses, which buses make the individual t... | 11/07/2006 |
| 7117285 | Method and system for efficiently directing interrupts A method and system for efficiently directing interrupts is disclosed. In a computer system having multiple processors, a computer implemented method, upon detecting an interrupt directed to one of the processors, determines a policy for efficiently handling the int... | 10/03/2006 |
| 7111090 | Method and system for identyfing a peripheral device by a high priority device-specific notification handler Method and system for latency-independent peripheral device identification. In one embodiment, a computer system receives an interrupt from a peripheral device coupled to a computer system communications port. In response, an interrupt notification message is posted... | 09/19/2006 |
| 7109747 | Low power, high speed logic controller that implements thermometer-type control logic by utilizing scan flip-flops and a gated clock The power dissipation, logic complexity and chip area of a thermometer controller are all significantly reduced by utilizing a series of scan flip-flops that are connected together to form a bi-directional shift register, along with a gated clock signal that clocks ... | 09/19/2006 |
| 7050830 | System with IC card deactivation The device, and a respective system, comprises a microcontroller for signal processing and an interface controller for communicating with an IC card, the interface controller being coupled between the microcontroller and the IC card. According to the invention, the ... | 05/23/2006 |
| 7047155 | Bus interface A bus interface connects a device to a bus that connects a plurality of devices to one another. The bus interface described is distinguished in that a timer provided in the bus interface or a timer provided in the chip that contains the bus interface is used to asce... | 05/16/2006 |
| 7043575 | Bus function authentication method, apparatus and computer program Devices connected to a communications bus are selectively accessed to the bus that communicates between one or more devices and a host machine. On the basis of analyzed device characteristics, communication between the device and the host machine via the bus is enab... | 05/09/2006 |
| 7038505 | Configurable enabling pulse clock generation for multiple signaling modes Enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse clock generator configurable to so generate the enabling pulse clocks. ... | 05/02/2006 |
| 7032049 | Apparatus for relaying received interrupt requests An apparatus is described which is distinguished by the fact that the apparatus does not output an interrupt request until after a plurality of interrupt requests have been received. The apparatus outputs a plurality of interrupt requests in response to an interrupt... | 04/18/2006 |
| 6965919 | Processing of unsolicited bulk electronic mail The present invention involves detecting unsolicited electronic mail distributed in bulk. In one embodiment, a method for automatically processing electronic mail loads an electronic mail message. Non non-textual information is removed from the electronic mail messa... | 11/15/2005 |
| 6963934 | Hibernation of computer systems An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including c... | 11/08/2005 |
| 6944739 | Register bank A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and co... | 09/13/2005 |
| 6931474 | Dual-function computing system having instant-on mode of operation A single, dual form computing device is provided that incorporates the functionality of a laptop computer with that of a handheld or palm-size computing device, and allows each functionality to be selectively employed. The dual form computing device operates in one ... | 08/16/2005 |
| 6931433 | Processing of unsolicited bulk electronic communication The invention relates to processing of electronic text communication distributed in bulk. In one embodiment, a method for detecting electronic text communication distributed in bulk is disclosed. After receiving a first electronic text communication, it is processed... | 08/16/2005 |
| 6922764 | Memory, processor system and method for performing write operations on a memory region A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit... | 07/26/2005 |
| 6910105 | Associative memory having a mask function for use in a network router When one or more storage data are coincident with single search data (12), an associative memory (1) carries out logical sum for all of storage data with a valid state for storage data as true. The result of logical sum is used as matched data logical-... | 06/21/2005 |
| 6883037 | Fast data decoder that operates with reduced output buffer bounds checking Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on e... | 04/19/2005 |
| 6865644 | System and method for industrial controller with an I/O processor using cache memory to optimize exchange of shared data A system and method for industrial control I/O forcing is provided. The invention includes a processor, shared memory and an I/O processor with cache memory. The invention provides for the cache memory to be loaded with I/O force data from the shared memory. The I/O... | 03/08/2005 |
| 6845409 | Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices A switch is presented including a host input/output (I/O) port adapted for coupling to a controller, multiple device I/O ports each adapted for coupling to at least one device, and logic coupled between the host I/O port and the device I/O ports configured to select... | 01/18/2005 |
| 6839857 | Interrupt controller in an interface device or information processing system There is disclosed an interface device which can prevent the freezing of an information processing system caused occupation of a system bus even when a wait signal outputted from the PC card is kept asserted. When the wait signal outputted from the PC card, is asser... | 01/04/2005 |
| 6823402 | Apparatus and method for distribution of signals from a high level data link controller to multiple digital signal processor cores In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a pac... | 11/23/2004 |
| 6816933 | Serial device daisy chaining method and apparatus A method to enable unique identification of serial devices having a common bus for communication with a bus master includes the step of serially clocking a mask value through a plurality of serial devices until each serial device stores a corresponding portion of th... | 11/09/2004 |
| 6816916 | Data storage system having multi-cast/unicast A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors.... | 11/09/2004 |
| 6813689 | Communications architecture for a high throughput storage processor employing extensive I/O parallelization A storage processor for a block storage RAID array services disk storage block requests from one or more hosts. At its heart, a application specific integrated chip (ASIC) supports a store and forward data transfer regime in that host to disk transfers are made by p... | 11/02/2004 |
| 6742060 | Look-up table based circuitry for sharing an interrupt between disk drive interfaces An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device... | 05/25/2004 |
