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| Number | Title | Issue Date |
| 7962673 | Method and apparatus for accessing a data bus to transfer data over the data bus A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a pe... | 06/14/2011 |
| 7757019 | Mobile hub and managing events in a mobile hub A mobile hub is proposed, the mobile hub includes a circular buffer for storing events, a timer for monitoring the storage period of an event stored in the buffer, and an event manager designed for discarding an event from the buffer when a time-out of the associate... | 07/13/2010 |
| 7680966 | Memory interface including generation of timing signals for memory operation A memory device includes an interface controller for communication with a semiconductor device over a communication link. A clock signal is transmitted from the semiconductor device over the link to the memory device. A frequency of the clock signal may be any withi... | 03/16/2010 |
| 7512724 | Multi-thread peripheral processing using dedicated peripheral bus One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a command message specifying a peripheral operation. A processing slice ... | 03/31/2009 |
| 7421521 | System, method and device for real time control of processor A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may, for example, be indicated by a signal from, for example, a slot timer,... | 09/02/2008 |
| 7373438 | System and method for reprioritizing high-latency input/output operations A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/... | 05/13/2008 |
| 7365869 | Image forming apparatus An image forming apparatus includes a first memory for storing image data, a second memory for storing image forming conditions, an image output unit for outputting the image data stored in the first memory under the image forming conditions stored in the second mem... | 04/29/2008 |
| RE40261 | Apparatus and method of partially transferring data through bus and bus master control device A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; d... | 04/22/2008 |
| 7359945 | Using conditional statements in electronic messages to prevent overuse of resources or time when delivering the electronic message A originating computing system sends an electronic message to a destination computing system via a routing path that includes one or more intermediary message processing computing systems. The originating computing system includes information in the electronic messa... | 04/15/2008 |
| 7343525 | Method and apparatus of detecting error of access wait signal A method and an apparatus for detecting an error of an access wait signal are disclosed. The method comprises the steps of accessing the input/output (I/O) device according to an I/O control command of the electronic device to access the I/O device; and returning to... | 03/11/2008 |
| 7340545 | Distributed peer-to-peer communication for interconnect busses of a computer system There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to establish an isochronous channel between a first device and a second de... | 03/04/2008 |
| 7313742 | Logic circuitry having self-test function A logic circuit having a self-test function includes a plurality of F/Fs having at least first-, second- and last-stage scanning F/Fs, each having a clock input, a scanning input and a scanning output terminals. The scanning F/Fs are connected one another so as to s... | 12/25/2007 |
| 7299308 | Data transmission apparatus and electronic control unit An electronic control unit has two microcomputers. Each microcomputer has a data buffer storing data first to be transmitted in every 8 ms, a second data buffer storing data to be transmitted in every 16 ms, and a third data buffer storing data to be transmitted in ... | 11/20/2007 |
| 7263573 | Wireless USB hardware scheduling In a wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high error rate experienced with wireless USB. Periodic transfers are fir... | 08/28/2007 |
| 7243173 | Low protocol, high speed serial transfer for intra-board or inter-board data communication A method and a circuit for converting parallel CPU information buses within circuit boards to serial data buses, while limiting overhead data to provide a low-level protocol and high rates of data transfer over distances up to forty inches. Larger scale parallel dat... | 07/10/2007 |
| 7191273 | Method and apparatus for scheduling a resource to meet quality-of-service restrictions The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is i... | 03/13/2007 |
| 7185123 | Method and apparatus for allocating bandwidth on a transmit channel of a bus A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus having a transmit channel, a receiving component, and a sending component configured to broadcast a payload to the receiving component ... | 02/27/2007 |
| 7181607 | Storage control apparatus In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be proces... | 02/20/2007 |
| 7146439 | Management of background copy task for point-in-time copies A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and background operations for predetermined time slots based on an indicator of ... | 12/05/2006 |
| 7139860 | On chip network with independent logical and physical layers An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each proces... | 11/21/2006 |
| 7124270 | Transceiver with latency alignment circuitry A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the ... | 10/17/2006 |
| 7120858 | Method and device for off-loading message digest calculations A method and device for off-loading from an application program the calculation of a data-integrity-checking value for specified data in a computer system. The data may be included in a message together with the integrity-checking value or may be in a portion of a m... | 10/10/2006 |
| 7093256 | Method and apparatus for scheduling real-time and non-real-time access to a shared resource A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time request can be completed before the latest possible start time at which a f... | 08/15/2006 |
| 7093038 | Application program interface-access to hardware services for storage management applications A method and device for using a set of APIs are provided. Some of the functions which used to be performed by software are now accelerated through hardware. ... | 08/15/2006 |
| 7085865 | I/O throughput by pre-termination arbitration The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that t... | 08/01/2006 |
| 7085205 | Recording and/or reproducing apparatus A recording and/or reproducing apparatus for causing data recorded on a first recording medium to be stored in a second recording medium. This recording and/or reproducing apparatus includes a reproducing unit for reading out data from the first recording medium at ... | 08/01/2006 |
| 7076573 | Method, apparatus, and program for detecting sequential and distributed path errors in MPIO An error detection mechanism is provided for detecting sequential and distributed errors in a device I/O stream. The sensitivity of the errors is user definable. The result of the error detection is fed back into the path management software, which may use the error... | 07/11/2006 |
| 7072530 | Semiconductor memory apparatus A semiconductor memory apparatus according to the present invention includes: two bank areas each having one-port memories capable of performing writing and reading only with separate timings; a writing control circuit for writing data into said one-port memories in... | 07/04/2006 |
| 7072996 | System and method of transferring data between a processing engine and a plurality of bus types using an arbiter A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a streaming interface. The I/O interface includes a streaming interface ... | 07/04/2006 |
| 7069122 | Remote locomotive control A locomotive control system includes an on-board controller responsive to a time signal received from a remote source for outputting a first polling signal at a time determined with reference to the time signal. A first remote controller is responsive to the polling... | 06/27/2006 |
| 7065580 | Method and apparatus for a pipelined network A computer system coupled with a pipelined network includes a plurality of initiator nodes coupled to send packets into the network. A plurality of target nodes receive packets sent into the network. The network uses a plurality of pipeline stages to transmit data a... | 06/20/2006 |
| 7065596 | Method and apparatus to resolve instruction starvation Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period. ... | 06/20/2006 |
| 7065622 | Transceiver with latency alignment circuitry A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers store... | 06/20/2006 |
| 7050446 | Communication control device and method A communication control device includes a determination circuit for determining whether reception of an asynchronous packet from an IEEE 1394 serial bus is allowed or denied by comparing the sum of the size of the asynchronous packet to be received and the size of p... | 05/23/2006 |
| 7032056 | Encoding of message onto strobe signals Methods and apparatus are disclosed for use in an electronic system where data is transmitted over signaling conductors from one electronic component to another using strobe signals accompanying the data. The edge or transition of the strobe signals identifies when,... | 04/18/2006 |
| 7028118 | Multi-channel buffered serial port debugging In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The complexity of generating interleaved TDM serial data from multiple source... | 04/11/2006 |
| 7010658 | Transceiver with latency alignment circuitry In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmi... | 03/07/2006 |
| 7003640 | Power-aware adaptation in an information server An information server with power-aware adaptation that enables power reduction while minimizing the performance impact of power reduction. An information server according to the present techniques includes a transaction prioritizer that determines which of a set of ... | 02/21/2006 |
| 6970986 | Software based system and method for I/O chip hiding of processor based controllers from operating system An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IO... | 11/29/2005 |
| 6965966 | Disk drive pre-computing seek parameters for a continuation track and a next command to facilitate continuing a read-ahead or aborting the read-ahead A disk drive is disclosed which pre-computes first seek parameters to seek to a continuation track storing read-ahead data, and second seek parameters to seek to a target track of a next command. An abort window is also computed for aborting a read-ahead operation e... | 11/15/2005 |
