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| Number | Title | Issue Date |
| 8171187 | System and method for arbitrating between memory access requests A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to... | 05/01/2012 |
| 8156263 | Information processing apparatus and storage device control method An information processing apparatus includes: a processor configured to run an operating system; a plurality of storage devices connected to the processor; a detection module configured to detect a boot process for installing the operating system; a determination mo... | 04/10/2012 |
| 8117359 | Memory control apparatus and method A memory control apparatus generates a plurality of commands whose unit of data transfer is smaller than the unit of data transfer of a memory access request, and when the memory access requests are transmitted from a plurality of request sources, issues the plurali... | 02/14/2012 |
| 8037219 | System for handling parallel input/output threads with cache coherency in a multi-core based storage array A system comprising a scheduler, a first core, and a second core. The scheduler may be configured to prioritize a plurality of input/output (IO) requests. The first core may be configured to process one of the plurality of IO requests based on the prioritizing of th... | 10/11/2011 |
| 8010719 | Virtual machine system Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virt... | 08/30/2011 |
| 8006004 | Non-intrusive debug port interface A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least on... | 08/23/2011 |
| 7979603 | Storage system and method for controlling activation of command A storage system including a queue corresponding to each priority level of command and an activation order control part. A command received from a host is accumulated in the queue corresponding to the specified priority. The activation order control part decides the... | 07/12/2011 |
| 7966434 | Detailed description of the preferred embodiments Disclosed is a printing apparatus including a priority identifier establishment unit. More particularly, the printing apparatus, processing an instruction designated by a priority identifier before another instruction, includes the priority identifier establishment ... | 06/21/2011 |
| 7945715 | System for data transfer between microcomputer devices The system according to the present invention for data transfer between microcomputer devices contains a standard protocol controller, a generally known ethernet controller, for example, as a coupling device instead of the known multipart RAM. Instead of a parallel ... | 05/17/2011 |
| 7853736 | Extending existing request commands of IEEE 1394 by adding extended request command having highest priority A data transfer device arranged in a node for connection in compliance with a communication standard. The data transfer device includes a request signal generation circuit for generating request signals defined by the communication standard with different levels of ... | 12/14/2010 |
| 7797467 | Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to encode a priority of a plurality of input signals. The second circuit may be configured to generate the plurality of input signals in response to one or more signals... | 09/14/2010 |
| 7797468 | Method and system for achieving fair command processing in storage systems that implement command-associated priority queuing In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonab... | 09/14/2010 |
| 7721023 | I/O address translation method for specifying a relaxed ordering for I/O accesses An I/O address translation method for specifying relaxed ordering for I/O accesses are provided. With the apparatus and method, storage ordering (SO) bits are provided in an I/O address translation data structure, such as a page table or segment table. These SO bits... | 05/18/2010 |
| 7664893 | Media drive control system and method Media drive control system and method. The media drive control system comprises a player console, a user operation filter, and a plurality of playback management devices. The player console provides an instant user operation (UOP) according to a received user comman... | 02/16/2010 |
| 7660919 | System and method for dynamically assigning I/O priority A system for controlling I/O transfers includes a host system or initiator including an adapter driver layer; and a storage controller. The storage controller includes a priority store and an operation queue. The adapter driver is selectively responsive to a datapat... | 02/09/2010 |
| 7657671 | Adaptive resilvering I/O scheduling In general, the invention relates to a method for storing data. The method includes receiving an Input/Output (I/O) request to store data in a storage pool, determining whether the I/O request is a resilvering I/O request, if the I/O request is a resilvering I/O req... | 02/02/2010 |
| 7644204 | SCSI I/O coordinator A Small Computer System Interface (SCSI) input/output (I/O) coordinator of an apparatus in an example caches in memory local to the SCSI I/O coordinator one or more I/O request contexts stored in memory non-local to the SCSI I/O coordinator. ... | 01/05/2010 |
| 7644205 | System and method for SAM-3 prioritization in iSCSI using 802.1q ethernet prioritization One embodiment of the present invention sets forth a technique for mapping a small computer system interface (SCSI) architecture model-3 (SAM-3) task priority to an IEEE Standard 802.1q tag control information (TCI) field. Four bits that define a SAM-3 task priority... | 01/05/2010 |
| 7555577 | Data transfer apparatus with channel controller and transfer controller capable of slave and standalone operation A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues data transfer requests. The transfer controller includes separate control of data source and data destination in a data... | 06/30/2009 |
| 7478179 | Input/output priority inheritance wherein first I/O request is executed based on higher priority A method for executing input/output (I/O) operations based on priority involves receiving a first I/O request for a unit of data, receiving a second I/O request for the same unit of data, determining a priority of the first I/O request and a priority of the second I... | 01/13/2009 |
| 7426621 | Memory access request arbitration A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the ... | 09/16/2008 |
| 7426583 | Method and circuit for decoding an address of an address space Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ran... | 09/16/2008 |
| 7409506 | Multiprocessor system with high-speed exclusive control A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and ... | 08/05/2008 |
| 7409476 | System and method for USB controllers A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. A... | 08/05/2008 |
| 7392353 | Prioritization of out-of-order data transfers on shared data bus Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers ... | 06/24/2008 |
| 7383360 | Electronic data storage system divides command requiring data transfer into subcommands, in accordance with performance of devices An electronic system includes two or more peripheral devices or units each of which is electronically coupled to the host through a single port of a predetermined bus. By splitting commands from the host to at least one of the two or more peripheral units into subco... | 06/03/2008 |
| 7380032 | Storage system, and method for controlling the same Disclosed is a method A method for controlling a storage system including a host computer; a first storage controller connected communicably to the host computer, for receiving a data frame transmitted from the host computer and executing data input to and data outp... | 05/27/2008 |
| 7373436 | Storage control device and method for management of storage control device A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the... | 05/13/2008 |
| 7373438 | System and method for reprioritizing high-latency input/output operations A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/... | 05/13/2008 |
| 7370161 | Bank arbiter system which grants access based on the count of access requests Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and al... | 05/06/2008 |
| 7366833 | Method and system for enhanced scheduling of memory access requests In information storage systems in which data retrieval requires movement of at least one physical element, a measurable amount of time is required to reposition that physical element in response to each data write or read request. After selecting one or more data re... | 04/29/2008 |
| 7366800 | System and method for dynamically assigning I/O priority A system for controlling I/O transfers includes a host system or initiator including an adapter driver layer; and a storage controller. The storage controller includes a priority store and an operation queue. The adapter driver is selectively responsive to a datapat... | 04/29/2008 |
| 7363391 | Storage system for queuing I/O commands and control method therefor A conventional storage system immediately executes a received I/O command because of importance of response time. Provided is a storage system which is coupled to a network and executes an I/O command received from at least one host computer through the network, in ... | 04/22/2008 |
| 7356631 | Apparatus and method for scheduling requests to source device in a memory access system An apparatus and method for scheduling requests to a source device is provided. The apparatus comprises a high-priority request queue for storing a plurality of high-priority requests to the source device; a low-priority request queue for storing a low-priority requ... | 04/08/2008 |
| 7353311 | Method of accessing information and system therefor A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority am... | 04/01/2008 |
| 7353349 | Method and apparatus for reordering memory requests for page coherency A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams b... | 04/01/2008 |
| 7346713 | Methods and apparatus for servicing commands through a memory controller port In a first aspect, a first method is provided for servicing commands. The first method includes the steps of (1) receiving a first command for servicing in a memory controller including a plurality of memory ports, wherein the first command is of a first priority; (... | 03/18/2008 |
| 7340539 | Device connected to a bus for storing information utilized to allocate priority to data stored in storage device and method for operating the device A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage (i.e., memories or memory areas) in which data to be transmitted or received is temporarily stored, and a... | 03/04/2008 |
| 7340542 | Data processing system with bus access retraction A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of... | 03/04/2008 |
| 7337285 | Buffer allocation based upon priority An information recording apparatus according to the present invention manages a priority value for each host that can log in, and allocates an immediate data buffer to each host based on the priority value. The priority value changes in accordance with data transfer... | 02/26/2008 |
