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| Number | Title | Issue Date |
| 8166337 | Failure analysis apparatus Relating with board numbers of the boards mounted with the logic circuits and mounted places on the boards and in relation to log information to be collected from the logic circuits, analysis information describing information to be processed when the log informatio... | 04/24/2012 |
| 8131883 | Method for distributing content to a user station A method for controlling a user station configured for communications with a multiplicity of independently-operated data sources via a non-proprietary network includes steps for providing a user interface to enable a user at the user station to select multiple ones ... | 03/06/2012 |
| 8060658 | Auto addressing devices on a common power and communication bus structure and method therefor A method for auto-addressing a device in communication with a controller is disclosed. The method includes communicating a pulse from a first contact of a controller, receiving the pulse at a second contact of a device in communication with the controller, communica... | 11/15/2011 |
| 7945703 | Matrix architecture for KVM extenders A matrix architecture for KVM extenders connecting a plurality of console terminals and a plurality of computers. The matrix architecture for KVM extenders includes a plurality of first extenders and a plurality of second extenders. The first extenders transform key... | 05/17/2011 |
| 7904603 | Adaptable datapath for a digital processing system The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN s... | 03/08/2011 |
| 7779165 | Scalable method for producer and consumer elimination Producers and consumer processes may synchronize and transfer data using a shared data structure. After locating a potential transfer location that indicates an EMPTY status, a producer may store data to be transferred in the transfer location. A producer may use a ... | 08/17/2010 |
| 7752339 | Matrix architecture for KVM extenders A matrix architecture for KVM extenders connecting a plurality of console terminals and a plurality of computers. The matrix architecture for KVM extenders includes a plurality of first extenders and a plurality of second extenders. The first extenders transform key... | 07/06/2010 |
| 7606943 | Adaptable datapath for a digital processing system The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN su... | 10/20/2009 |
| 7555568 | Method and apparatus for operating a host computer from a portable apparatus The present invention provides methods and apparatus that utilize a portable apparatus to operate a host computer. The portable apparatus including an operating system and a list of software applications is installed in a removable data storage medium. The basic inp... | 06/30/2009 |
| 7444437 | Input/output device and method of setting up identification information in input/output device An input/output device and a method of setting up identification information for an input/output device, to confirm which slot of which device enclosure each unit is mounted in, within a short time, from a map, and execute quick access to the unit. A unit mounted on... | 10/28/2008 |
| 7444440 | Method and device for providing high data rate for a serial peripheral interface An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. ... | 10/28/2008 |
| 7426607 | Memory system and method of operating memory system A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the m... | 09/16/2008 |
| 7408661 | Control apparatus and its method, and control program and storage medium holding it, with access designating second address being performed based on link to the second address included in display information A controller which exists between a client apparatus and an image processing apparatus and which controls access from the client apparatus such that the client apparatus can use a network server function of the image processing apparatus, its control method and cont... | 08/05/2008 |
| 7395380 | Selective snooping by snoop masters to locate updated data A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originat... | 07/01/2008 |
| 7386635 | Electronic device circuit having a sensor function for expandably connecting a plurlity of electronic devices An electronic device (120) includes: an input connector (121), including at least three address pins and plural data pins; a function chip (123), including address pins and data pins corresponding to those of the input connector, and directly co... | 06/10/2008 |
| 7386619 | System and method for allocating communications to processors in a multiprocessor system In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment. ... | 06/10/2008 |
| 7376810 | Integrated device with multiple reading and/or writing commands An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the ad... | 05/20/2008 |
| 7373439 | System method using material exchange format (MXF) converting program for audio and video data files having routines that generates attribute data from audio and video data file An MXF parser thread 43 parses data MXF_D, being, mixed together, a plurality of video data PIC, a plurality of audio data SOU, and system data SYS. Then, it generates video file attribute data VFPD concerning the video based on the parsed system data and met... | 05/13/2008 |
| 7373565 | Start/stop circuit for performance counter A circuit for tracking a number of clock cycles between occurrences of an event of interest. The circuit includes logic for asserting a run signal responsive to a first occurrence of the event of interest, logic for deasserting the run signal responsive to a second ... | 05/13/2008 |
| 7373448 | Method, system, and program for building a queue to test a device Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from accessing the bus. An initiator transmits I/O requests on the bus to th... | 05/13/2008 |
| 7370348 | Technique and apparatus for processing cryptographic services of data in a network system A controller for controlling communications between a system and a transport medium includes a receiving circuit to receive data and associated security control information. A first cryptographic engine cryptographically processes the data received from the transpor... | 05/06/2008 |
| 7370142 | Command control method in network storage system Without setting a specific function to a disk device and adding a specific function to disk access commands, a command control method for limiting an address range to be targets of the commands to be capable of optimizing an execution order of the commands, and a ne... | 05/06/2008 |
| 7366803 | Integrated circuit for buffering data by removing idle blocks to create a modified data stream when memory device is not near empty A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of co... | 04/29/2008 |
| 7366843 | Computer system implementing synchronized broadcast using timestamps A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by the active device, an address network for conveying address packets b... | 04/29/2008 |
| 7363440 | System and method for dynamically accessing memory while under normal functional operating conditions A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maint... | 04/22/2008 |
| 7360026 | Method and apparatus for synchronizing data with a reduced clock cycle response time A data buffering unit includes a memory that stores data from a data transmitting device. The data buffering unit also includes a memory read manager that prepares data stored in the memory for output prior to receiving a request for the data from a data reading dev... | 04/15/2008 |
| 7356627 | Device identification A data handling device capable of operating in a system in which two or more devices are connected by a data bus for the transmission of communications therebetween, the data bus having two or more data lines and the device having: two or more data bus connectors, e... | 04/08/2008 |
| 7346051 | Slave device, master device and stacked device A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements... | 03/18/2008 |
| 7343451 | Disk array device and remote copying control method for disk array device Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional interference between the split units is prevented and stable remote co... | 03/11/2008 |
| 7334151 | Method of and device for detecting cable connection using an oscillation circuit and a counter The detector includes the plug for connecting the personal computer through a cable, battery power supply which provides a constant power supply, and the MCU which receives a specific potential from the personal computer when the later is connected. ... | 02/19/2008 |
| 7331791 | System and method for evaluating a person's information technology skills An IT skills evaluation system and method for evaluating an individual's IT skills. According to one aspect of the invention, the individual is required to perform one or more practical exercises. A practical exercise is an evaluation device for evaluating not only ... | 02/19/2008 |
| 7328286 | Automatic addressing on bus systems In a method and apparatus for automatic address allocation among control devices connected to a bus system in a vehicle, and address allocation period sending a message on the common data bus line. During the address allocation period, the common data bus line is br... | 02/05/2008 |
| 7325086 | Method and system for multiple GPU support Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coup... | 01/29/2008 |
| 7315308 | Methods and system for merging graphics for display on a computing device Disclosed are methods and systems that allow video applications to merge their outputs for display and to transform the outputs of other applications before display. A graphics arbiter tells applications the estimated time when the next frame will be displayed on a ... | 01/01/2008 |
| 7315307 | Methods and systems for merging graphics for display on a computing device Disclosed are methods and systems that allow video applications to merge their outputs for display and to transform the outputs of other applications before display. A graphics arbiter tells applications the estimated time when the next frame will be displayed on a ... | 01/01/2008 |
| 7302509 | Method and data structure for random access via a bus connection A method for addressing cells in devices via an I2C bus is suggested, in which the common addressing scheme is supplemented by a ‘Data Transfer Mode’ byte. The ‘Data Transfer Mode’ byte specifies the number of the address and data bytes to follow the device ... | 11/27/2007 |
| 7302503 | Memory access engine having multi-level command structure A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer fi... | 11/27/2007 |
| 7302546 | Method, system, and article of manufacture for reserving memory Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wher... | 11/27/2007 |
| 7295134 | Terrain avoidance method and device for an aircraft An aircraft terrain avoidance method and device may employ a collision warning section that transmits a caution signal when the aircraft risks colliding with the terrain at the end of a first predetermined period of time. A warning signal is transmitted when the air... | 11/13/2007 |
| 7296094 | Circuit and method to provide configuration of serial ATA queue depth versus number of devices Disclosed is a system using a SAS host controller and SAS expanders to control multiple SATA end devices where the memory contained on the SAS host controller is fixed to ease the cost and power consumption of the SAS host controller device, but where there is an ex... | 11/13/2007 |
