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A vest or belt is integrally formed with tubular, pet receiving passageways which extend around the wearer's body and terminate in pocket-like chambers for feeding and retrieval.
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| Number | Title | Issue Date |
| 8145805 | Method for re-sequencing commands and data between a master and target devices utilizing parallel processing Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the t... | 03/27/2012 |
| 8145806 | Storage-side storage request management Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on a one or more logical characteristics of the I/O requests. The logical characteristics may include, for ... | 03/27/2012 |
| 8140348 | Method, system, and program for facilitating flow control Disclosed is a technique for flow control. It is detected that a work request is being transferred to an in-memory structure. A maximum limit is compared with a number of work requests stored in the in-memory structure. If the number of work requests stored in the i... | 03/20/2012 |
| 8108573 | Apparatus, system, and method for enqueue prioritization An apparatus, system, and method are disclosed for enqueue prioritization. The apparatus for enqueue prioritization is provided with a plurality of modules configured to functionally execute the necessary steps of anticipating a need to access a computing resource, ... | 01/31/2012 |
| 8055816 | Memory controllers, memory systems, solid state drives and methods for processing a number of commands The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command que... | 11/08/2011 |
| 8024498 | Transitions between ordered and ad hoc I/O request queueing Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The... | 09/20/2011 |
| 8006003 | Apparatus, system, and method for enqueue prioritization An apparatus, system, and method are disclosed for enqueue prioritization. The apparatus for enqueue prioritization is provided with a plurality of modules configured to functionally execute the steps of holding one or more queued requests in a queue, sorting the qu... | 08/23/2011 |
| 7853735 | Efficient processing of groups of host access requests that may include zero length requests This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host... | 12/14/2010 |
| 7844758 | Dynamic resource allocation scheme for efficient use of a queue A method and mechanism for managing requests to a resource. A request queue receives requests from multiple requestors and maintains a status for each requestor indicating how many requests the requestor has permission to issue. Upon initialization, the request queu... | 11/30/2010 |
| 7774356 | Method and apparatus for application state synchronization A method and an apparatus that synchronize an application state in a client with a data source in a backend system in an asynchronous manner are described. A response is sent to the client based on a priority determined according to a history of received update requ... | 08/10/2010 |
| 7707332 | I/O-request processing system and method An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section (501) receives an I/O request issued from an external device ( | 04/27/2010 |
| 7613850 | System and method utilizing programmable ordering relation for direct memory access A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cac... | 11/03/2009 |
| 7447811 | Storage device, storage control firmware activation program exchange method, and program product for activating and exchanging storage control program A storage control device 2A includes a host interface control unit 3, a storage control firmware A, and electrically rewritable non-volatile memory 7 and, using non-volatile memory 7, stores necessary information during exchange of an act... | 11/04/2008 |
| 7437493 | Modular architecture for a network storage controller A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be... | 10/14/2008 |
| 7426603 | Memory bus arbitration using memory bank readiness A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapa... | 09/16/2008 |
| 7426621 | Memory access request arbitration A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the ... | 09/16/2008 |
| 7424579 | Memory controller for processor having multiple multithreaded programmable units A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control ... | 09/09/2008 |
| 7418526 | Memory hub and method for providing memory sequencing hints A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses ... | 08/26/2008 |
| 7418540 | Memory controller with command queue look-ahead In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random Access Memory (RAM) and selecting one of the commands based, at least in ... | 08/26/2008 |
| 7418543 | Processor having content addressable memory with command ordering A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to read-modify-write commands. ... | 08/26/2008 |
| 7412594 | Method and apparatus for managing data access and storage of data located on multiple storage devices An apparatus and method for accessing a data item from a storage system having a plurality of data storage devices are disclosed. I/O operation requests are submitted to multiple data storage devices for each data item to be accessed. The I/O operation requests are ... | 08/12/2008 |
| 7404058 | Method and apparatus for avoiding collisions during packet enqueue and dequeue A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or stat... | 07/22/2008 |
| 7386636 | System and method for communicating command parameters between a processor and a memory flow controller A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controlle... | 06/10/2008 |
| 7373448 | Method, system, and program for building a queue to test a device Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from accessing the bus. An initiator transmits I/O requests on the bus to th... | 05/13/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366801 | Method for buffering work requests Disclosed is a technique for buffering work requests. It is determined that a work request is about to be placed into an in-memory structure. When the in-memory structure is not capable of storing the work request, a work request ordering identifier for the work req... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7366813 | Event queue in a logical partition An information processing system is provided which includes a plurality of system resources, and an event queue having a predetermined number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events i... | 04/29/2008 |
| 7363440 | System and method for dynamically accessing memory while under normal functional operating conditions A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maint... | 04/22/2008 |
| 7363412 | Interrupting a microprocessor after a data transmission is complete A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives ... | 04/22/2008 |
| 7363391 | Storage system for queuing I/O commands and control method therefor A conventional storage system immediately executes a received I/O command because of importance of response time. Provided is a storage system which is coupled to a network and executes an I/O command received from at least one host computer through the network, in ... | 04/22/2008 |
| 7363389 | Apparatus and method for enhanced channel adapter performance through implementation of a completion queue engine and address translation engine A method and apparatus for enhancing channel adapter performance that includes a host interface, a link interface, a packet processing engine, an address translation engine, and a completion queue engine. The host interface is connected to a memory by a local bus. T... | 04/22/2008 |
| 7363399 | Method, apparatus and computer program product providing storage network dynamic tuning of I/O flow with Queue Depth In accordance with a computer program product, apparatus and a method there is provided a redundant network wherein a host computer operates with a plurality of storage devices by monitoring conditions of the multipath storage network and controlling a storage multi... | 04/22/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7356631 | Apparatus and method for scheduling requests to source device in a memory access system An apparatus and method for scheduling requests to a source device is provided. The apparatus comprises a high-priority request queue for storing a plurality of high-priority requests to the source device; a low-priority request queue for storing a low-priority requ... | 04/08/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7350013 | Bus communication apparatus for programmable logic devices and associated methods A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry ... | 03/25/2008 |
| 7342934 | System and method for interleaving infiniband sends and RDMA read responses in a single receive queue A system and method for processing interleaved Sends of encapsulated communications and responses to RDMA Reads in a single InfiniBand queue pair receive queue. The queue is implemented as one or more linked lists of memory buckets, and stores Send commands (contain... | 03/11/2008 |
