Bizarre Patents
A kissing shield comprised of a thin, flexible membrane and a frame or holder.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5261055 | Externally updatable ROM (EUROM) An electronically programmable read-only memory module has an embedded micro-controller for program/data updating. Upon power up, the module acts as a prior art ROM. The embedded micro-controller in a standby mode is responsive to data arriving from a dow... | 11/09/1993 |
| 5206943 | Disk array controller with parity capabilities A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility i... | 04/27/1993 |
| 5193169 | Image data processing apparatus An image data processing apparatus has: a reading portion for reading an image of an original and outputting the image data thereon, an encoding portion for encoding the image data which has been output from the reading portion, an image memory for storin... | 03/09/1993 |
| 5133054 | Data transmission apparatus for autonomously and selectively transmitting data to a plurality of transfer path A data transmission apparatus including an input-side data transmission path having a first-stage data transmission path, a second-stage data transmission path and a plurality of output-side data transfer paths is provided. When data, which include an ide... | 07/21/1992 |
| 5084837 | FIFO buffer with folded data transmission path permitting selective bypass of storage A first-in first-out type memory is used as a buffer for data transfer between asynchronous systems. This buffer memory has a minimum delay elastic buffer function in which the number of data storage stages is changed according to the data transfer situat... | 01/28/1992 |
| 5070477 | Port adapter system including a controller for switching channels upon encountering a wait period of data transfer A port adapter for an input/output system for a large data processing system. The port adapter is coupled to an I/O processor of that system and also to main memory of the system so that when the port adapter is selected by a system interrupt message from... | 12/03/1991 |
| 5060134 | Action direction port expansion circuit and system Circuitry is provided which effectively expands one, and preferably two or more, high resolution timed outputs of a microprocessor device such that a larger number of output signals are selectively, and independent of one another, switched to output state... | 10/22/1991 |
| 5014197 | Assignment of files to storage device using macro and micro programming model which optimized performance of input/output subsystem A practical mathematical algorithm is used to solve the so-called "File Assignment Problem" (FAP). The FAP is partitioned into two sequential optimization problems, called the macro model and the micro model. The macro model is solved by a Non-Linear Prog... | 05/07/1991 |
| 4825406 | Secondary storage facility employing serial communications between drive and controller In a system including a plurality of mass storage devices at least one of which includes first and second ports, a plurality of controllers and cables coupling the ports to various ones of the controllers and in which each device can only be on-line throu... | 04/25/1989 |
| 4821179 | Communication system configuration detection apparatus and method A data processing system includes a processor unit (CPU) connected over a CPU bus to a plurality of memory components, but is not connected to any input-output (I/O) component of the system. The system I/O component(s) connect to the memories over an I/O ... | 04/11/1989 |
| 4747047 | Data transfer system using two peripheral controllers to access dual-ported data storage units A data transfer network includes a group of disk drive peripheral units, each has dual ports for connection to two separate peripheral-controllers. A host computer can initiate either peripheral-controller to access selected disk drive units for Read/Writ... | 05/24/1988 |
| 4672535 | Multiprocessor system In a multiprocessor system of the type in which two or more separate processor modules are connected by an interprocessor bus dedicated exclusively to interprocessor communication for parallel processing, there is provided an input/output system having mu... | 06/09/1987 |
| 4649470 | Data processing system A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second, or "vertical", microinstruction portions in a vertical microcontrol stor... | 03/10/1987 |
| 4644462 | Input/output interrupt system A data processing system having a channel processing device provided with an input/output device which requires input/output interrupt. The channel processing device responding to a request for input/output interrupt, propagating the request for input/out... | 02/17/1987 |
| 4604682 | Buffer system for interfacing an intermittently accessing data processor to an independently clocked communications system A buffer system for interfacing an intermittently accessing data processor to a communications system in which the transfer of data bits is clocked at a predetermined rate in response to clock pulses provided by a communications system clock signal. The s... | 08/05/1986 |
| 4455605 | Method for establishing variable path group associations and affiliations between "non-static" MP systems and shared devices Multiprocessing systems having changeable CPU configurations generate unique changeable identifications (ID's). These are presented by I/O channels over various I/O connection paths, in association with special path defining commands and function data. Re... | 06/19/1984 |
| 4437157 | Dynamic subchannel allocation An apparatus for and a method of Dynamic Subchannel Allocation permitting easily field modifiable assignment of Input/Output (I/O) subchannels to I/O channels. Many present day medium-to-large scale computers have an I/O unit(s) with a fixed number of I/O... | 03/13/1984 |
| 4435755 | Balanced channel finding method For a CPU I/O request, the disclosed methods find a physical channel path within a logical channel (LCH) likely to be connectable to a requested device by using channel path count (CAT count) fields. The CAT counts respectively indicate the current number... | 03/06/1984 |
| 4413317 | Multiprocessor system with cache/disk subsystem with status routing for plural disk drives In a data processing system having plural disk devices connected to first and second storage control units, and plural processors connected to the storage control units by connection paths, a table is provided having entries defining the connection paths ... | 11/01/1983 |
| 4396984 | Peripheral systems employing multipathing, path and access grouping A data-processing system is connected to a peripheral system by a plurality of channel paths. These channel paths are named as members of path groups. Each path group has one or more channel paths. Within each path group, communications between the data-p... | 08/02/1983 |
| 4374415 | Host control of suspension and resumption of channel program execution Apparatus is provided to permit a processor to interrupt computer input/output operations and later resume the same operations. The apparatus disconnects the input/output device involved in the operations from the channel to free the channel for other ope... | 02/15/1983 |
| 4313162 | I/O Subsystem using data link processors An input-output subsystem for relieving the housekeeping functions of a main host computer and for controlling and transferring data between selected peripheral terminal units and the main host computer. The host computer system connects to a base module ... | 01/26/1982 |
| 4207609 | Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system A method and means for path independent reservation and reconnection of devices to CPU's operating in a multi-CPU and shared device access system environment. The multi-CPU and shared device access system comprises a plurality of sets of fan out paths (ch... | 06/10/1980 |
| 4181934 | Microprocessor architecture with integrated interrupts and cycle steals prioritized channel A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one o... | 01/01/1980 |
| 4176341 | Information transfer apparatus An information transfer apparatus for connecting between plural channels and input/output control devices in a computer system, comprising a bundle of signal lines with which said channels are connected, said bundle of signal lines including plural signal... | 11/27/1979 |
| 4133029 | Data processing system with two or more subsystems having combinational logic units for forming data paths between portions of the subsystems A data processing system constituted by at least two subsystems, each having at least an integrated combinational logic unit comprising a storage and input/output gates and with which at least two control units are connected. The subsystems are constructe... | 01/02/1979 |
| 4060849 | Data input and output controller There is disclosed an input/output controller for an information processing system comprising a main memory, a central processing unit, a peripheral controller and a plurality of peripheral units coupled to the central processing unit. In particular, the ... | 11/29/1977 |
| 4047157 | Secondary storage facility for data processing A controller for use in a data processing system for coupling a direct access storage element to the system. The controller contains a control path for routing control information from the system to various circuits in the controller and designated storag... | 09/06/1977 |
| 4001784 | Data processing system having a plurality of input/output channels and physical resources dedicated to distinct and interruptible service levels In a data processing system having a plurality of input/output channels, a first plurality of physical resources is dedicated to each of the channels. Said first plurality is sufficient only to enable standard data character exchanges between each of the ... | 01/04/1977 |
