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"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
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| Number | Title | Issue Date |
| 8171186 | On-chip interconnect fabric A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also c... | 05/01/2012 |
| 8156262 | Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. ... | 04/10/2012 |
| 8046505 | Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features A memory controller including an address incrementer and a page crossing detect logic. The address incrementer may be configured to generate a next address in a burst from a current address in the burst. The page crossing detect logic may be configured to determine ... | 10/25/2011 |
| 8041855 | Dual-bus system for communicating with a processor A system for communicating with a processor within an integrated circuit can include a dual-bus adapter (115) coupled to the processor (105) through a first communication channel (110) and a second communication channel (120). The dual-bu... | 10/18/2011 |
| 8019913 | Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. ... | 09/13/2011 |
| 7984207 | Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. ... | 07/19/2011 |
| 7962669 | Memory controller and memory control method A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception circuit. The transmission circuit transmits a first data of a first bit length for a first burst times by ... | 06/14/2011 |
| 7899955 | Asynchronous data buffer The present invention relates to an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems. The asynchronous data buffer comprises a data memory for storing m data elements of a data burst and a valid bit memor... | 03/01/2011 |
| 7861014 | System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to th... | 12/28/2010 |
| 7802027 | Method for data processing in a scan microscope comprising a fast scanner and scan microscope comprising a fast scanner The process acquires data blocks in real-time with a fast scanner. The acquired data blocks are then transmitted to a computer system (23). The data blocks are then processed as a function of a frame burst ratio (N). The transmission of the acquired data bloc... | 09/21/2010 |
| 7779174 | Method and apparatus for dynamically changing burst length using direct memory access control A direct memory access controlling method includes checking a length value of remaining data corresponding to data remaining after transmission of the data stored in the source memory to the destination memory, and a currently set burst length value, comparing the l... | 08/17/2010 |
| 7711873 | Bandwidth control and power saving by interface aggregation A first processor that executes at least one application or process includes a first interface module that interfaces the first processor to a second processor and that includes N interfaces. N is an integer greater than 1. The first processor also includes a first ... | 05/04/2010 |
| 7707328 | Memory access control circuit A data transfer request of a data pro cessing device with respect to a synchronous memory is divided by a burst transfer length unit request dividing section into a plurality of data transfer requests in which a data transfer amount is an amount of data to be burst-... | 04/27/2010 |
| 7657669 | Apparatus and program storage device for managing dataflow through a processing system A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus. ... | 02/02/2010 |
| 7627700 | Expanded memory for communications controller One embodiment of the present invention includes a communication system. The system comprises a communications controller configured to control transmission and reception of communications data in a network. The system also comprises a memory configured to store con... | 12/01/2009 |
| 7603493 | Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. ... | 10/13/2009 |
| 7587529 | Method for controlling memory in mobile communication system Disclosed is a method for controlling a memory in a mobile communication system. The method includes receiving certain frame control information by a Data Receiver Block (DRB) from a MAP decoder, forming a burst descriptor by the DRB by using the frame control infor... | 09/08/2009 |
| 7584308 | System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to ... | 09/01/2009 |
| 7555576 | Processing apparatus with burst read write operations A digital signal processing system comprises a programmable processor (PROC) and a peripheral device (PD, MEM) coupled to the programmable processor via a burst generation device (BG). The processor is arranged to communicate with the peripheral device using a read ... | 06/30/2009 |
| 7543088 | Various methods and apparatuses for width and burst conversion Methods and apparatuses are described for a communication system. The communication system comprises an initiator core supporting a first burst capability as well as a target core supporting a second burst capability. The supported burst features of the second burst... | 06/02/2009 |
| 7523230 | Device and method for maximizing performance on a memory interface with a variable number of channels The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memor... | 04/21/2009 |
| 7475168 | Various methods and apparatus for width and burst conversion Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core. The communication system may also include two or more target agents, ... | 01/06/2009 |
| 7461183 | Method of processing a context for execution A method and apparatus in a data controller in a storage drive for retrieving, evaluating, and processing a context that describes a direct memory access (DMA) request. The data controller includes a buffer for storing data transferred in response to execution of a ... | 12/02/2008 |
| 7434009 | Apparatus and method for providing information to a cache module using fetch bursts Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) l... | 10/07/2008 |
| 7418535 | Bus system and method of arbitrating the same A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one trans... | 08/26/2008 |
| 7409471 | Data transfer control device for data transfer over a bus, electronic equipment and method for data transfer over a bus When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF p... | 08/05/2008 |
| 7404017 | Method for managing data flow through a processing system A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus. ... | 07/22/2008 |
| 7398335 | Method and system for DMA optimization in host bus adapters Method and system for optimizing DMA request processing is provided. The system includes a HBA that uses a dynamic DMA maximum write burst count sizing to optimize processing of write and read requests, wherein the HBA includes a DMA optimizer module that selects a ... | 07/08/2008 |
| 7392329 | System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The method comprises establishing a status block for a plurality of devices t... | 06/24/2008 |
| 7380027 | DMA controller and DMA transfer method A DMA channel data quantity setting section sets a data transfer quantity of each of a plurality of DMA channels in accordance with a data quantity or a ratio in advance. A channel select control circuit determines whether each DMA channel is active. A data transfer... | 05/27/2008 |
| 7376763 | Method for transferring data from a memory subsystem to a network adapter by extending data lengths to improve the memory subsystem and PCI bus efficiency A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a c... | 05/20/2008 |
| 7376777 | Performing an N-bit write access to an M×N-bit-only peripheral A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a wr... | 05/20/2008 |
| 7366866 | Block size allocation in copy operations Described herein are exemplary storage network architectures and methods for block size allocation in copy operations. A copy operation from a first storage cell to a second storage cell is initiated. The copy operation initially utilizes a first write block size. T... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| RE40261 | Apparatus and method of partially transferring data through bus and bus master control device A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; d... | 04/22/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7362948 | Video copying apparatus When execution of copying of video and audio from a DVD from a videotape is instructed, a video copying apparatus 1 detects the remaining amount of the videotape set in a apparatus and reproduction time of video and audio copied to the videotape and based on ... | 04/22/2008 |
| 7356605 | System and method for controlling delivery of streaming media A system and method for controlling delivery of streaming media include the capability to receive streaming media at an endpoint device at a first delivery rate and at the endpoint device, determine whether to adjust the first delivery rate and generate a command to... | 04/08/2008 |
| 7353357 | Apparatus and method for pipelined memory operations A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory ... | 04/01/2008 |
| 7334060 | System and method for increasing the speed of serially inputting data into a JTAG-compliant device A JTAG-compliant device is configured to receive data through the control (TMS) line in addition to being configured to receive data through the input (TDI) line. A burst-write instruction is made the active instruction, extending the capability of the test access p... | 02/19/2008 |
