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| Number | Title | Issue Date |
| 6988154 | Memory interface and method of interfacing between functional entities A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with ... | 01/17/2006 |
| 6988162 | High-speed router with single backplane distributing both power and signaling A high-speed, high-power modular router is disclosed. As opposed to conventional designs using optical backplane signaling and/or bus bars for power distribution, the disclosed embodiments combine high-power, low-noise power distribution with high-speed signal routi... | 01/17/2006 |
| 6981057 | Data storage with stored location data to facilitate disk swapping A first image processing system, a second image processing system, a first storage system and a second storage system communicate over a high bandwidth switch. The switch connects the first processing system to the first storage system and also connects the second p... | 12/27/2005 |
| 6981086 | Instrumentation system including a backplane having a switched fabric bus and instrumentation lines An instrumentation system which extends channel-based switched fabric architectures to provide instrumentation signaling functions. The system comprises a chassis including slots for receiving inserted modules. The chassis includes a backplane which provides for int... | 12/27/2005 |
| 6981090 | Multiple use of microcontroller pad A circuit arrangement permits a microcontroller wirebond pad to be configured to be an analog or digital input or output. The circuit arrangement uses any of a plurality of switching configurations to selectively determine the use of the wirebond pad under control o... | 12/27/2005 |
| 6978341 | Computer, a method of connecting devices to data bus controllers, a method of allocating the bandwidth of a plurality of data bus controllers and apparatus therefor A computer having a plurality of data bus controllers, a plurality of grouped controller ports and a plurality of connection elements for connecting the controllers to the ports, wherein each controller has a maximum available controller bandwidth; characterized in ... | 12/20/2005 |
| 6977656 | Two-layer display-refresh and video-overlay arbitration of both DRAM and SRAM memories A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines ... | 12/20/2005 |
| 6978340 | I/O multiplexer and pin controller with serial and parallel capabilities for microprocessor based engine control A controller 12 has an I/O crossover switching network 14, an optional I/O network expansion 16, a plurality of serial I/O shifters 18, a clock generator 20 and I/O control logic 22. The I/O crossover-switching network 14... | 12/20/2005 |
| 6976103 | Data migration method using storage area network A new disk system is connected to a switch that has been already connected to a host and old disk system. At that time, the new disk system is assigned in advance a port ID of the same value as the port ID that has been assigned to the F—Port of the swi... | 12/13/2005 |
| 6976114 | Method and apparatus for simultaneous bidirectional signaling in a bus topology A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a tran... | 12/13/2005 |
| 6976116 | Disk subsystem A protocol controller disposed between switches in a fiber channel fabric switch circuit and disk drive units for converting a protocol to enable one-to-one connectivity established between controllers and disk drive units. ... | 12/13/2005 |
| 6975553 | Nonaligned access to random access memory Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offse... | 12/13/2005 |
| 6973078 | Method and apparatus for implementing low latency crossbar switches with integrated storage signals A digital crossbar switch utilizes an asynchronous RAM to provide high density and low latency storage and a write enable pulse generator to generate write enable pulses that are independent of the clock signal duty cycles. The crossbar switch includes a plurality o... | 12/06/2005 |
| 6973315 | Method and system for sharing over-allocated bandwidth between different classes of service in a wireless network A method and system for sharing over-allocated bandwidth between different classes of service in a wireless network. Traffic is transmitted for a first service class in excess of bandwidth allocated to the first service class using unused bandwidth allocated to a se... | 12/06/2005 |
| 6970967 | Crossbar circuit having a plurality of repeaters forming different repeater arrangements A crossbar circuit (30, 40, 50, 60, 70, 80, 90, 100) having programmable repeater structures adapted to allow configuration of the crossbar with inputs at multiple sides of the crossbar die. A plurality of repeaters (62) are arranged in different repea... | 11/29/2005 |
| 6971043 | Apparatus and method for accessing a mass storage device in a fault-tolerant server An apparatus and method for accessing a first local mass storage device or a second local mass storage device in a fault-tolerant server. In one embodiment, the fault-tolerant server establishes communication between a first computing element and a first local mass ... | 11/29/2005 |
| 6970455 | Space/time switch architecture A switching core in accordance with the principles of the present invention connects N input ports to M output ports and provides multi-cast capability. The switching core includes a plurality of selection blocks, each of which receives multiple input bit packs orga... | 11/29/2005 |
| 6967999 | Method and apparatus to support multi standard, multi service base-stations for wireless voice and data networks An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically real... | 11/22/2005 |
| 6968442 | Parallel computer with improved access to adjacent processor and memory elements A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory elements. For example, the processing element which corresponds to a lo... | 11/22/2005 |
| 6968443 | Microprocessor The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of compo... | 11/22/2005 |
| 6967962 | Linking crossbar controller A data network including at least one crossbar, wherein each crossbar comprises N ports and a plurality N of devices each associated with and connected to one port of one of the crossbars. Each one port of one crossbar includes an input buffer, a plurality N−1 of ... | 11/22/2005 |
| 6968406 | System and method for arbitrating access between common access requests on a bus A system and method of arbitrating access on a bus includes a bus, a bus expander, a boot module, and a management module. The bus expander includes an access engine, a first bus interface, a second bus interface, and a plurality of general purpose input/output port... | 11/22/2005 |
| 6961803 | Sliced crossbar architecture with no inter-slice communication A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; i... | 11/01/2005 |
| 6961888 | Methods and apparatus for encoding LDPC codes Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identic... | 11/01/2005 |
| 6959355 | Universal serial bus hub with shared high speed handler A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ... | 10/25/2005 |
| 6959372 | Processor cluster architecture and associated parallel processing methods A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors as... | 10/25/2005 |
| 6956851 | Crossbar subsystem and method A system is disclosed for routing data cells from at least one of a plurality of source port processors to at least one destination port processor. Such a system contemplates each cell comprising a plurality of cell frame portions. In a preferred embodiment of the s... | 10/18/2005 |
| 6957375 | Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation Methods and apparatus of the present invention can be used to implement a communications system wherein different devices using the same LDPC code can be implemented using different levels of parallelism. The use of a novel class of LDPC codes makes such differences... | 10/18/2005 |
| 6956861 | Controlled shared memory smart switch system An interconnect structure comprising a plurality of input ports and a plurality of output ports with messages being sent from an input port to a predetermined output port through a switch S. Advantageously, the setting of switch S is not dependent upon the predeterm... | 10/18/2005 |
| 6957285 | Data storage system A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a plurality of directors interconnected through an interface state data bus and a plurality of end-... | 10/18/2005 |
| 6954821 | Crossbar switch that supports a multi-port slave device and method of operation A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address r... | 10/11/2005 |
| 6954281 | Method and apparatus for image processing, and a computer product A programmable image processor capable of realizing a plurality of image formation operations is comprised of an SIMD type data operation processing section, RAMs, memory controllers, and memory switches. The memory controller and the memory switches selectively con... | 10/11/2005 |
| 6950893 | Hybrid switching architecture A hybrid switching module includes a hybrid switching module processor data channel; a hybrid switching module main data channel; an input/output link data channel; a switch coupled to the hybrid switching module processor data channel; and a bridge coupled to the h... | 09/27/2005 |
| 6948031 | Methods and apparatus for transferring a data element within a data storage system The invention is directed to techniques for transferring data within a data storage system that includes, among other things, an interconnection mechanism having a point-to-point channel between an interface circuit (e.g., a director) and a volatile memory cache cir... | 09/20/2005 |
| 6941649 | Method of fabricating a high-layer-count backplane The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or gre... | 09/13/2005 |
| 6944702 | Data storage system A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface includes a backplane; a first printed circuit board plugged into a first side of the backplane; a second printed cir... | 09/13/2005 |
| 6940912 | Dynamically adaptive multimedia application program interface and related methods A method of interfacing non-integrated media processing system elements is presented, the method comprising identifying one or more characteristics of one or more media processing system elements, and dynamically negotiating which system elements will perform certai... | 09/06/2005 |
| 6940308 | Interconnection network for a field programmable gate array An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaran... | 09/06/2005 |
| 6934788 | Port expansion peripheral module system A user configurable, modular port expansion system allows the user of a host system such as a USB-enabled personal computer to customize a desired configuration of one or more peripheral device modules without the use of cables between modules. The peripheral device... | 08/23/2005 |
| 6934283 | System and method for source defined packet routing A data communication system and method are provided to communicate in a multiprocessor interconnection network or other network. In one embodiment, the present system includes a number of logical circuits that are located in a number of nodes interconnected in a mul... | 08/23/2005 |
