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Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
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| Number | Title | Issue Date |
| 5379441 | Homebus system for permitting homebus equipment and ISDN basic interface equipment to use same twisted pair line homebus A homebus system for permitting use of a twisted pair line homebus to both homebus equipment and integrated service digital network (ISDN) interface equipment. The homebus system includes a homebus controller for controlling access to the twisted pair lin... | 01/03/1995 |
| 5377333 | Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks and exchangers Crossbar switches having 2n +1 ports and computing clusters are arranged so that each crossbar switch is connected to 2n processors. Auxiliary processors that perform parallel processing administrative functions and input/output func... | 12/27/1994 |
| 5341509 | Parallel processing system including a stack of bus-printed disks and a plurality of radially exending processing unit boards Disclosed is a parallel processing system comprising, in combination, a stack assembly of bus-printed disks and a plurality of processing unit boards standing upright around and electrically connected to the stack assembly of bus-printed disks. Each bus-p... | 08/23/1994 |
| 5339396 | Interconnection network and crossbar switch for the same In a parallel computer including L=n1 x n2 x - - - x nN processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n1 +1/n | 08/16/1994 |
| 5331315 | Switch for serial or parallel communication networks A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodat... | 07/19/1994 |
| 5313590 | System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer A network and method for interconnecting a plurality of router elements in a parallel computer. The network forms a routing system for routing data from source processing elements to destination processing elements. The input lines and output lines of eac... | 05/17/1994 |
| 5313649 | Switch queue structure for one-network parallel processor systems A switch queue structure for one-network parallel processor systems minimizes chip count and reduces the possibility of deadlock which might otherwise occur with this type of switch structure. The switch queue structure comprises a plurality of input port... | 05/17/1994 |
| 5299317 | Method and apparatus for simulating an interconnection network A method and apparatus are described for simulating on one multi-stage interconnection network (MIN) the operation of a second MIN. By means of two algorithms we generate first and second vectors, I1, O1, which characterize the first... | 03/29/1994 |
| 5293489 | Circuit arrangement capable of centralizing control of a switching network In a circuit arrangement for use in accessing selected address numbered with a preselected distance left between two adjacent ones of the selected addresses, a control circuit centralizes control operation of a switching network with reference to a refere... | 03/08/1994 |
| 5274782 | Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconnection networks A method and apparatus for routing processor-memory data traffic in a shared-memory multiprocessor computer system employs an interconnection network including two buffered multistage switching networks. Each of these networks can be used to route the dat... | 12/28/1993 |
| 5261059 | Crossbar interface for data communication network An interface between a host computer and a crossbar switch is provided which employs data buffering using multiple-port RAM devices. The receive and transmit data is clocked into or out of separate serial ports of the RAM, and at the same time a local pro... | 11/09/1993 |
| 5247689 | Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments A digital computer system including a large number of parallel processing modules (PPM's). Each PPM includes an arithmetic logic unit (ALU), an instruction decoder, and internal bus switching. The main memory is organized in columns and rows with a separa... | 09/21/1993 |
| 5239629 | Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routin... | 08/24/1993 |
| 5226125 | Switch matrix having integrated crosspoint logic and method of operation There is disclosed a switch matrix and operational method relying upon a high degree of operational logic at each matrix crosspoint. In one embodiment, the switch is used in a multiprocessor system arranged as an image and graphics processor. The processo... | 07/06/1993 |
| 5179669 | Multiprocessor interconnection and access arbitration arrangement In a multiprocessor system (FIG. 1), the processors (10-12) are interconnected by a non-blocking communication medium such as a crossbar switch (19). Each processor is connected to a dedicated port circuit (18) at the switch by an optical link (16). Each ... | 01/12/1993 |
| 5175824 | Crossbar switch connected modular multiprocessor system with processor timing relationship selected and synchronized to be appropriate for function being performed This invention discloses a processing structure, and related method, for performing a selected data processing function by means of multiple processing modules that are selected to perform the selected function when appropriately connected together. The m... | 12/29/1992 |
| 5165023 | Parallel processing system with processor array and network communications system for transmitting messages of variable length A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the... | 11/17/1992 |
| 5134690 | Augumented multiprocessor networks An augmented De Bruijn multiprocessor network. Multiple microprocessors having a constant number of I/O ports are connected according to a network technique which yields a machine of predetermined degree. A modified binary De Bruijn graph of degree four, ... | 07/28/1992 |
| 5101480 | Hexagonal mesh multiprocessor system An interconnection network for a plurality of process nodes, each illustratively comprised of a processor-memory pair, utilizes an hexagonal mesh arrangement of size n which is wrapped in each of the x, y, and z directions. In accordance with the inventio... | 03/31/1992 |
| 5081575 | Highly parallel computer architecture employing crossbar switch with selectable pipeline delay A crossbar switch which connects N (N=2k ; k=0, 1, 2, 3) coarse grain processing elements (rated at 20 million floating point operations per second) to a plurality of memories provides for a parallel processing system free of memory conflicts o... | 01/14/1992 |
| 5072366 | Data crossbar switch A crossbar switch consists of a control computer, and a switching matrix which includes a number of switching cells in which connections between data input lines and data output lines are made. The switch operates to simultaneously connect to data output ... | 12/10/1991 |
| 5058053 | High performance computer system with unidirectional information flow A high performance computer system with a plurality of processors and memory modules is arranged with the processor modules stacked one upon the other with first switch modules in a first stack and with the memory modules stacked one on the other with sec... | 10/15/1991 |
| 5055997 | System with plurality of processing elememts each generates respective instruction based upon portions of individual word received from a crossbar switch A data processor system having at least one arithmetic/logic processor element and at least one memory processor element which can be coupled in circuit using a crossbar switch. The arithmetic/logic processor element is provided with an ALU and a program ... | 10/08/1991 |
| 5053942 | Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system A cross-connect circuit for coupling each of a plurality of processors to a memory module selected from a plurality of such modules, provided the module in question has not been identified for connection to another of the processors is disclosed. The circ... | 10/01/1991 |
| 4982187 | Low-end high-performance switch subsystem architecture An architecture for a low-end, high-performance switch subsystem allows the connection of a multitude of requests per link. The switch subsystem operates a cross-bar switch under the control of a controller, such as a personal computer, to connect selecte... | 01/01/1991 |
| 4858113 | Reconfigurable pipelined processor The reconfigurable pipelined processor includes a plurality of memory devices and arithmetic units interconnected by cross bars for transferring raw and processed data therebetween. A counter is connected with the cross bar to provide a source of addresse... | 08/15/1989 |
| 4811210 | A plurality of optical crossbar switches and exchange switches for parallel processor computer A computer (30) has parallel elementary processors (P1, . . . , PK) interconnected by an optical crossbar switch (32). Multiple groups of processors, each having a separate crossbar switch, are connected by exchange switches. Optical fibers (34) are used ... | 03/07/1989 |
| 4807183 | Programmable interconnection chip for computer system functional modules The interconnection chip of the present invention is a custom chip which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports. The chip includes a crossbar interconnec... | 02/21/1989 |
| 4654780 | Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result... | 03/31/1987 |
| 4633386 | Digital signal processor A digital signal processor (10) has a crossbar network (110) interconnecting a control and timing circuit (100), a multiplier (112), a serial access data memory (128), temporary storage registers (122, 124, 126), an accumulator (120) and input and output ... | 12/30/1986 |
| 4014005 | Configuration and control unit for a heterogeneous multi-system A configuration and control unit (CACU) is described for a heterogeneous multi-system containing processors which may be of different types, channels, one or more channel crossbar switches which may be of different sizes, various I/O channel switches, I/O... | 03/22/1977 |
| 3984819 | Data processing interconnection techniques The disclosure describes an interconnection switching matrix for a data processing system which includes system resource units or processor units. Each processor unit is equipped with an interface and has the ability to control the switching matrix either... | 10/05/1976 |
| 3949374 | Arrangement for supplying input signals to central processing units without interruption of programs A read-out signal generator supplies read-out signals through a read-out bus bar to sources of first data signals and buffer memories storing second data signals produced by accompanying central processing units (CPU's) to make the read-out bus bar transm... | 04/06/1976 |
