Bizarre Patents
Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 5974239 | Data transfer method for a bus device in a computer system by placing first and second addresses corresponding to a bridge and with the bus device respectively on a bus A PCI/ISA computer system architecture is disclosed in which the ISA legacy circuitry (such as the interrupt request controller, DMA controller, and timer counter unit) is integrated within the system controller coupling the processor and PCI buses. Accor... | 10/26/1999 |
| 5970234 | PCI bus arbiter and a bus control system having the same A PCI bus arbiter is provided as an additional PCI bus in PCI peer-to-peer bus bridge system. A bus control system having the PCI bus arbiter is also provided. The bus control system includes bus masters, a first PCI bus bridge, a second PCI bus bridge, a... | 10/19/1999 |
| 5937173 | Dual purpose computer bridge interface for accelerated graphics port or registered peripheral component interconnect devices A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional registered peripheral component int... | 08/10/1999 |
| 5937174 | Scalable hierarchial memory structure for high data bandwidth raid applications A cache memory control architecture within a RAID storage subsystem which simplifies the migration and porting of existing ("legacy") control methods and structures to newer high performance cache memory designs. A centralized high speed cache memory is c... | 08/10/1999 |
| 5918025 | Method and apparatus for converting a five wire arbitration/buffer management protocol into a two wire protocol A method for converting signals from one arbitration and management protocol to another. The conversion is performed by at least three state machines. The conversion circuit converts a set of signals on the first bus to a bus request signal on the second ... | 06/29/1999 |
| 5898888 | Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system A method and system for translating peer-to-peer access across multiple Peripheral Component Interconnect (PCI) host bridges within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and ... | 04/27/1999 |
| 5892931 | Method and apparatus for splitting a bus target response between two devices in a computer system The present invention provides a method and apparatus for splitting a bus target response between two devices in a computer system. In one embodiment, the computer system includes a bus having a first signal line and a second signal line, a third signal l... | 04/06/1999 |
| 5889970 | Dual purpose apparatus, method and system for accelerated graphics port and peripheral component interconnect A core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional peripheral component interconnect ("PCI") bus an... | 03/30/1999 |
| 5884053 | Connector for higher performance PCI with differential signaling An enhanced PCI bus architecture utilizing differential signaling is supported by an adapter slot connector providing differential signaling pins and a make-before-break connection between bus conductors and dummy loads for each bus conductor, enabling hi... | 03/16/1999 |
| 5854910 | Method for accessing control and status registers across a peer-peer bus A method for performing a data transfer to one of a plurality of peripheral devices in a computer system comprising a first bus, a bus bridge for coupling to the first bus and for interfacing to a second bus, the second bus coupled to the bus bridge, and ... | 12/29/1998 |
| 5854908 | Computer system generating a processor interrupt in response to receiving an interrupt/data synchronizing signal over a data bus A computer system having interrupts synchronized to data storage by having an interrupt data signal (interrupt packet) follow the path of the data to an interrupt receiver, which interrupts the processor to execute an interrupt service routine. Rather tha... | 12/29/1998 |
| 5793995 | Bus system for shadowing registers The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bri... | 08/11/1998 |
| 5781748 | Computer system utilizing two ISA busses coupled to a mezzanine bus A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the... | 07/14/1998 |
| 5778197 | Method for allocating system resources in a hierarchical bus structure The system resources in a computer system having a multi-level, hierarchical bus structure are allocated by determining the address resource requirement of the devices and lower level PCI-PCI bridges, if any, subordinate to every higher level bridge by re... | 07/07/1998 |
| 5771387 | Method and apparatus for interrupting a processor by a PCI peripheral across an hierarchy of PCI buses A number of remote I/O ICUs, enhanced PCI--PCI bridges, and an ICC bus interface unit are distributively provided to a computer system having a processor and an hierarchy of PCI buses for facilitating PCI agents coupled to the lower level PCI buses to int... | 06/23/1998 |
| 5764933 | Deadlock prevention in a two bridge system by flushing write buffers in the first bridge A method for preventing deadlocks is used in a computing system in which a host bus is connected to a first input/output bus through a first bridge and the first input/output bus is connected to a second input bus through a second bridge. When transferrin... | 06/09/1998 |
| 5761448 | Physical-to-logical bus mapping scheme for computer systems having multiple PCI bus configuration A Plug-and-Play (PnP) configuration driver initilization routine and PnP configuration utility for use in PCI bus architectures supporting dynamic I/O bus configurations. The PnP configuration driver includes a logical-to-physical PCI bus mapping scheme m... | 06/02/1998 |
| 5721931 | Multiprocessing system employing an adaptive interrupt mapping mechanism and method A symmetrical multiprocessing system is provided that includes a central interrupt control unit. The central interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt sources include a plur... | 02/24/1998 |
| 5682509 | Bus interface to a RAID architecture A file server system provides increased bandwidth between a processor, a memory and a redundant array of inexpensive disks (RAID). The file server includes a processor connected to a processor bus. A first bridging circuit couples the processor bus to a p... | 10/28/1997 |
| 5664117 | Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to ... | 09/02/1997 |
| 5632021 | Computer system with cascaded peripheral component interconnect (PCI) buses A system including primary and secondary PCI (Peripheral Component Interconnect) buses which do not "livelock". The system includes two PCI to PCI bridges between the primary and secondary buses. One of the bridges is configured to only act as a target on... | 05/20/1997 |
| 5630145 | Method and apparatus for reducing power consumption according to bus activity as determined by bus access times A power conservation computer architecture is provided for disabling a clock signal to all peripheral devices and bus controllers located on a plurality of Peripheral Component Interconnect (PCI) buses when it is determined that all of the PCI buses are i... | 05/13/1997 |
| 5396602 | Arbitration logic for multiple bus computer system An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory... | 03/07/1995 |
| 5379384 | Configuration data loopback in a bus bridge circuit A method and apparatus for reducing cost and complexity of devices in a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back "bridged" configuration data to access configuration registers.... | 01/03/1995 |
| 5359715 | Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots... | 10/25/1994 |
| 4468733 | Multi-computer system with plural serial bus loops A multi-computer system includes a plurality of data processors and at least one I/O device which is commonly accessible by the data processors. A plurality of serial bus loops are configurated in hierarchy with interbus linkage devices disposed between a... | 08/28/1984 |
