Bizarre Patents
Pet Toilet-Like Water Disk and Food Storage
One pet-friendly inventor patented "a device for watering pets, e.g., a dog or cat." The device, he helpfully noted, "has the general shape of a toilet."
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| Number | Title | Issue Date |
| 6636919 | Method for host protection during hot swap in a bridged, pipelined network In a bridged, pipelined network (FIG. 1), a network-to-host bridge (140) identifies the address space of a host computer (FIG. 2) as not being contained within the host computer memory space (120). During the removal of the host computer (100) and its rep... | 10/21/2003 |
| 6606675 | Clock synchronization in systems with multi-channel high-speed bus subsystems A high-speed bus subsystem includes a plurality of bus channels, wherein each bus channel has an independent channel clock signal generated by an associated channel clock generator. A master device or other interface component receives and utilizes a syst... | 08/12/2003 |
| 6598092 | Trunk transmission network In a trunk transmission network for transmitting information signals between nodes via paths, flexible path operation is achieved by setting up paths between source nodes and destination nodes after pre-classifying paths into a higher service class in whi... | 07/22/2003 |
| 6587868 | Computer system having peer-to-peer bus bridges and shadow configuration registers A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a ran... | 07/01/2003 |
| 6584538 | Information processing system An information processing system is configured such that which when an application handling multimedia, especially, moving images is performed by an information processor such as a personal computer, a sufficient processing performance is realized with th... | 06/24/2003 |
| 6581129 | Intelligent PCI/PCI-X host bridge A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data... | 06/17/2003 |
| 6557067 | System and method to effectively compensate for delays in an electronic interconnect A system and method to effectively compensate for delays in an electronic interconnect comprises a controller that initially schedules a first transmission from a first talker device to several listener devices. The controller then schedules a second talk... | 04/29/2003 |
| 6553430 | Computer system implementing flush operation A computer system is presented which implements a "flush" operation providing a response to a source which signifies that all posted write operations previously issued by the source have been properly ordered within their targets with respect to other pen... | 04/22/2003 |
| 6549972 | Method and system for providing control accesses between a device on a non-proprietary bus and a device on a proprietary bus A method for providing control accesses between a device on a non-proprietary bus and a device on a proprietary bus is disclosed. A gateway controller is connected between a proprietary bus and a non-proprietary bus. A message originated from a device on ... | 04/15/2003 |
| 6519657 | Method and device for identifying an active 1394A node attached to a 1394B network A method and device for identifying that a 1394a node is actively attached to a 1394b network and indicating so to the 1394b network. In one embodiment, a border node first determines that a 1394a node is actively attached to the border node. Then, the bo... | 02/11/2003 |
| 6519671 | Method of network configuration, method and apparatus for information processing, and computer-readable media A bridge manager (bridge management equipment) is automatically determined. In a network, bridges 51 to 54 are configured by connecting portals 41 to 48 respectively connected to buses 11 to 15 and the different buses 11 to 15 are connected via the bridge... | 02/11/2003 |
| 6502158 | Method and system for address spaces A system for allowing a node to be accessed through multiple address spaces. The system includes a virtual address memory providing a software settable bus identification address and a stable node identification address for each node in a net, a physical ... | 12/31/2002 |
| 6463483 | Low latency input-output interface A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The system also includes a device bus, which may or may not be... | 10/08/2002 |
| 6457139 | Method and apparatus for providing a host computer with information relating to the mapping of logical volumes within an intelligent storage system Method and apparatus directed to a computer system including a host computer and an intelligent storage system that stores data accessed by the host computer, the computer system including a plurality of logical volumes of data that are visible to the hos... | 09/24/2002 |
| 6457083 | Communication on non-continuously sampled lines A communication channel that is accessible when the product is entirely assembled, but appears to be, and functions like, configuration jumpers to the end user. The communication channel utilizes the terminals of a configuration jumper block as communicat... | 09/24/2002 |
| 6453368 | Adding a dummy data or discarding a portion of data in a bus repeater buffer memory for a second data transfer to a second bus A first bus 11 and a second bus 12 are connected through a bus repeater 13 having a buffer memory, and DMA (Direct Memory Access) controllers 22, 27 are respectively connected to the buses 11 and 12. The bus repeater 13 can issue DMA request to the respec... | 09/17/2002 |
| 6442514 | Method and system for simulating a communications bus A method and system for simulation of a communications bus. A simulation arrangement is configured with a behavioral agent and an application agent coupled to the bus. Bus commands are selectively loaded in the behavioral and application agent in accordan... | 08/27/2002 |
| 6442137 | Apparatus and method in a network switch for swapping memory access slots between gigabit port and expansion port A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports... | 08/27/2002 |
| 6430710 | Data processing system with RAS data acquisition function In an information processing system having a bus bridge connected between a plurality of buses for data transfer therebetween, the bus bridge is provided with a RAS data acquisition bus operating independently from the plurality of buses and a RAS data ac... | 08/06/2002 |
| 6388586 | Method for reversing the bits of a computer data structure The bits comprising a computer data structure are reversed rapidly and efficiently using a combination of data partitioning and table look ups. In an exemplary embodiment, the invention is employed in the pre-processing of Advanced Configuration and Power... | 05/14/2002 |
| 6330629 | Information processing system An information processing system is configured such that which when an application handling multimedia, especially, moving images is performed by an information processor such as a personal computer, a sufficient processing performance is realized with th... | 12/11/2001 |
| 6321286 | Fault tolerant computer system A computer system includes an apparatus which enables transactions directed to a particular target device such as one situated inside a bridge to be shunted directly to the device without requiring that the transaction actually proceed to the device throu... | 11/20/2001 |
| 6298409 | System for data and interrupt posting for computer devices A system for monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The system employs a fabric controller to manage transaction commands among and host devices. The system employs an inter... | 10/02/2001 |
| 6279065 | Computer system with improved memory access A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a writ... | 08/21/2001 |
| 6275885 | System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues pla... | 08/14/2001 |
| 6266728 | Network system having a bridge that assigns identification numbers to buses connected as a tree and that reserves some identification numbers When many buses are provided, addition/omission of a bus frequently occurs. Whenever the addition/omission of the bus occurs, a configuration process of the overall network system must be performed. Thus, interruption of data communication occurs frequent... | 07/24/2001 |
| 6260094 | Method and apparatus providing programmable decode modes for secondary PCI bus interfaces A PCI-to-PCI having programmable decode modes comprising at least one of a standard bridge data transfer transaction, an intelligent bridge data transfer transaction, and a private address space data transfer transaction, and wherein the transactions are ... | 07/10/2001 |
| 6253275 | Interrupt gating method for PCI bridges A method and apparatus for managing interrupt requests from devices on a subordinate bus is disclosed. An interrupt request storage area is provided on the bridge device to allow the bridge device to log and track interrupt requests. Once an interrupt req... | 06/26/2001 |
| 6240480 | Bus bridge that provides selection of optimum timing speed for transactions An improved bus bridge in a computer system for connecting a first data bus and a second data bus, said bus bridge having means for connecting said first and second buses, means for receiving an address representing a transaction on said first bus, means ... | 05/29/2001 |
| 6233637 | Isochronous data pipe for managing and manipulating a high-speed stream of isochronous data flowing between an application and a bus structure An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any... | 05/15/2001 |
| 6233638 | System for configuring peer devices A system for configuring peer devices without unnecessary delay in boot up time by using a compatibility bridge. Upon initiating a configuration cycle, a BIOS initialization scans all peer devices located on the host bus. A watchdog timer times out after ... | 05/15/2001 |
| 6226703 | Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU'S with write-back caches An apparatus is provided for reducing read latency for an I/O device residing on a bus having a short read latency timeout period. The apparatus includes a I/O bridge on an I/O bus having a longer read latency timeout which modifies read transactions into... | 05/01/2001 |
| 6226700 | Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansi... | 05/01/2001 |
| 6223240 | Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices The method and apparatus provides a data processing system. The data processing system includes a primary bus, a secondary bus, and a host processor connected to the primary bus. The data processing system includes a first secondary processor connected to... | 04/24/2001 |
| 6219738 | Information processing system In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module ... | 04/17/2001 |
| 6219739 | Spanning tree with fast link-failure convergence The Spanning Tree Protocol converges to a new configuration after the loss of a link. A new frame, known as a root link query request BPDU is transmitted to the root bridge in the spanning tree when a bridge detects an indirect link failure through the re... | 04/17/2001 |
| 6216190 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the CPU bus for controlling the transfer of cycles from the CPU to the perip... | 04/10/2001 |
| 6202114 | Spanning tree with fast link-failure convergence The Spanning Tree Protocol converges to a new configuration after the loss of a link. A new frame, known as a root link query request BPDU is transmitted to the root bridge in the spanning tree when a bridge detects an indirect link failure through the re... | 03/13/2001 |
| 6199134 | Computer system with bridge logic that asserts a system management interrupt signal when an address is made to a trapped address and which also completes the cycle to the target address A computer system includes a South bridge logic that connects an expansion bus to one or more secondary expansion busses and peripheral devices. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. Th... | 03/06/2001 |
| 6195719 | Bus system for use with information processing apparatus A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connect... | 02/27/2001 |
