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"What, sir, would you make a ship sail against the wind and currents by lighting a bonfire under her deck? I pray you, excuse me, I have not the time to listen to such nonsense."
Napoleon Bonaparte ; When told of the Robert Fulton steamboat
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| Number | Title | Issue Date |
| 8117371 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 02/14/2012 |
| 8112571 | Signal connection device and method A device may include a first data path coupled between a first port and a data transfer section that enables data paths between the first data path and at least a second port and a third port. A second data path may be coupled between the first port and the second p... | 02/07/2012 |
| 8046516 | Cache coherent switch device In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transaction... | 10/25/2011 |
| 8041872 | Enabling multiple devices using a single bus bridge Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a processor that translates different routing numbers received from the bus into different addres... | 10/18/2011 |
| 8032684 | Programmable bridge header structures A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. Th... | 10/04/2011 |
| 8019924 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 09/13/2011 |
| 7991939 | Dummy accesses to ensure CPU exits lower-power state Circuits, methods, and apparatus that provide transactions to wake an external device from a low-power state before a data transfer. This prevents an interruption that would be caused if the external device exited the low-power state during the data transfer. One ex... | 08/02/2011 |
| 7987312 | Method and apparatus for dynamically determining bit configuration A method for dynamically determining bit configuration for a host bridge. The method first obtains information of peripheral components coupled to the host bridge. Next, the method dynamically determines a bit configuration of a processor system bus connecting to th... | 07/26/2011 |
| 7984225 | ASCII gateway to in-vehicle networks ASCII gateway to in-vehicle system provides bi-directional translation between multiplexed motor vehicle networks and industrial control and monitoring devices. Integrated hardware and software components provide data communications between motor vehicle electronic ... | 07/19/2011 |
| 7945721 | Flexible control and/or status register configuration A register access request for control and/or status operations from a link is detected using a hardware mechanism and is forwarded to a software-controlled entity for access to a virtual register for control and/or status operations. The software-controlled entity c... | 05/17/2011 |
| 7921253 | Cache coherent switch device In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transaction... | 04/05/2011 |
| 7917680 | Performance based packet ordering in a PCI express bus A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement (100), such as a PCI Express type arrangement, carries out separate arbitration funct... | 03/29/2011 |
| 7904629 | Virtualized bus device A virtualization of the internal interconnection bus, which results in a virtualized switch or virtualized multi-ported bridge. In the case of a PCI Express switch, one embodiment includes virtualization of the undefined interconnection bus. In the case of a Multi-p... | 03/08/2011 |
| 7899969 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 03/01/2011 |
| 7865654 | Programmable bridge header structures A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. Th... | 01/04/2011 |
| 7853748 | Method and apparatus to obtain code data for USB device A method and apparatus are provided that include creating an image of a page descriptor at a universal serial bus (USB) device, transferring the image of the page descriptor to a main memory, modifying a schedule list in a main memory based on the transferred image,... | 12/14/2010 |
| 7822907 | Methods and apparatuses for serial bus sideband communications Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communication... | 10/26/2010 |
| 7797475 | Flexibly configurable multi central processing unit (CPU) supported hypertransport switching Embodiments of the invention address deficiencies of the art in respect to hypertransport-based switching for multi-CPU systems and provide a method, system and computer program product for flexibly configurable multi-CPU supported hypertransport switching. In one e... | 09/14/2010 |
| 7788440 | Method and device for coupling at least two independent bus systems There is described a method for coupling at least two independent bus systems and to a suitable device for carrying out said method, a cycle time TA, TB being assigned to each bus system and each data item from a sequence of data being transmit... | 08/31/2010 |
| 7765354 | Compressed report descriptors for USB devices A method and apparatus for creating USB peripheral device report descriptors: A short, compressed, report descriptor is stored in a peripheral device. This short report descriptor is transmitted to a USB wireless bridge and combined with templates stored in the brid... | 07/27/2010 |
| 7752376 | Flexible configuration space A configuration space operation packet is received from a link. The configuration space operation packet is detected using a hardware mechanism. The configuration space operation packet is forwarded to a software-controlled entity for processing. A received packet c... | 07/06/2010 |
| 7734857 | Cache coherent switch device In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transaction... | 06/08/2010 |
| 7707347 | Data path master/slave data processing device apparatus An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processin... | 04/27/2010 |
| 7698492 | Guaranteed services method and apparatus in bridged LAN Provided are a guaranteed services method and apparatus in bridged LAN. streams are transmitted through bridges to a plurality of listener stations in a distributed network, and each bridge performs filtering, stream group registration and authentication for the str... | 04/13/2010 |
| 7689756 | Apparatus and system for an address translation device An apparatus, system and method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The apparatus includes a detection module to detect an incoming... | 03/30/2010 |
| 7689755 | Apparatus and method for sharing devices between multiple execution domains of a hardware platform A method and apparatus for sharing peripheral devices between multiple execution domains of a hardware platform are described. In one embodiment, the method includes the configuration end-point devices, bridges and interconnects of a hardware platform including at l... | 03/30/2010 |
| 7660934 | ASCII gateway to in-vehicle networks ASCII gateway to in-vehicle system provides bi-directional translation between multiplexed motor vehicle networks and industrial control and monitoring devices. Integrated hardware and software components provide data communications between motor vehicle electronic ... | 02/09/2010 |
| 7660935 | Network bridge A network bridge with a configuration and control unit. The unit is connected to some or all of the functional components of the network bridge via interfaces. The unit may poll and evaluate data within the functional components, including operating data and/or para... | 02/09/2010 |
| 7660936 | Enabling multiple ATA devices using a single bus bridge Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addres... | 02/09/2010 |
| 7644220 | Programmable controller In a programmable controller including a special unit, a special-purpose integrated circuit element can be readily utilized for multiple purposes to extend the range of applications to reduce a manufacture cost. A special unit (130) connected to a microproces... | 01/05/2010 |
| 7610430 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 10/27/2009 |
| 7600068 | Programmable control interface device A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable int... | 10/06/2009 |
| 7596652 | Integrated circuit having processor and bridging capabilities An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor, a bridge, and circuitry capable of coupling the bridge and the processor to a first bus and to a second bus. The first bus may be compatible w... | 09/29/2009 |
| 7574550 | Guaranteed isochronous services method and apparatus in bridged LAN Provided are a guaranteed isochronous services method and apparatus in bridged LAN. Isochronous streams are transmitted through bridges to a plurality of listener stations in a distributed network, and each bridge performs filtering, stream group registration and au... | 08/11/2009 |
| 7526595 | Data path master/slave data processing device apparatus and method An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the dat... | 04/28/2009 |
| 7512731 | Computer system and memory bridge for processor socket thereof A multi-processor computer system includes a memory bridge configured in a processor socket on a motherboard. The memory bridge module electrically connects a processor bus and a memory bus that connect to the processor socket. Thus, an adjacent processor is capable... | 03/31/2009 |
| 7500046 | Abstracted host bus interface for complex high performance ASICs An interface is provided to couple an input/output device (e.g., a network interface unit) to one or more different host system buses without altering the configuration of the device (e.g., to include logic specific to the host buses). Functionality of the device (e... | 03/03/2009 |
| 7500045 | Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus... | 03/03/2009 |
| 7444453 | Address translation device A method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The method includes detecting an incoming address on the I2C bus, translating the inco... | 10/28/2008 |
| 7441066 | Managing a computer system having a plurality of partitions using a service processor The inventive multiple partition computer system allows the reconfiguration of the installed hardware, possibly while the various partitions continue normal operations. This aspect includes adding and removing process cell boards and I/O from partitions which may or... | 10/21/2008 |
