Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 7062592 | Selecting a queue for service in a queuing system In general, in one aspect, the disclosure describes an apparatus for selecting a queue from a plurality of queues. The apparatus includes a hierarchal queue occupancy device to indicate an occupancy status of the plurality of queues, a next queue selector to select ... | 06/13/2006 |
| 7062588 | Data processing device accessing a memory in response to a request made by an external bus master A data processing device exchanges data between a memory and an external bus master. The memory is connected to the data processing device via a first bus so as to store data. The external bus master is connected to the data processing device via a second bus so as ... | 06/13/2006 |
| 7058750 | Scalable distributed memory and I/O multiprocessor system A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network compris... | 06/06/2006 |
| 7058751 | Packet switch The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot... | 06/06/2006 |
| 7058064 | Queueing system for processors in packet routing operations In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inse... | 06/06/2006 |
| 7058797 | Use of off-motherboard resources in a computer system A system uses a protocol stack on a card external to a motherboard in a target computer system. A processor on the motherboard is able to make use of the external protocol stack during boot-up of the computer, or at any other time, so that it is not necessary to loa... | 06/06/2006 |
| 7054987 | Apparatus, system, and method for avoiding data writes that stall transactions in a bus interface A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource associated with servicing transaction requests to the targets, such as a posted write buffer. If a transactio... | 05/30/2006 |
| 7055005 | Methods and apparatus used to retrieve data from memory into a RAM controller before such data is requested A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The RAM controller may store such data into a prefetch buffer. ... | 05/30/2006 |
| 7054986 | Programmable CPU/interface buffer structure using dual port RAM Disclosed is a programmable buffer circuit (16) for interfacing a CPU (12) to a plurality of channel interfaces (14). The buffer circuit includes a dual port memory (18) having a first port coupled to a CPU data bus and a second port coup... | 05/30/2006 |
| 7054985 | Multiple hardware partitions under one input/output hub A method and a mechanism are capable of partitioning computer hardware components or elements at the level of individual processing paths, or ropes. Incoming and outgoing queues may be designed such that transactions to/from one rope do not interfere with another ro... | 05/30/2006 |
| 7054979 | Method and apparatus for routing configuration accesses from a primary port to a plurality of secondary ports The method of routing configuration accesses applied from the primary port to a plurality of secondary ports includes the steps of: distributing a plurality of configuration accesses received from the primary bus to the plurality of secondary ports in accordance wit... | 05/30/2006 |
| 7054971 | Interface between a host and a slave device having a latency greater than the latency of the host An interface between a host and a slave device having a latency greater than the latency of the host is disclosed. The interface includes a register and a state machine. The state machine provides data to the host from any address in the slave in two host read cycle... | 05/30/2006 |
| 7051162 | Methods and apparatus used to retrieve data from memory before such data is requested A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The memory controller may store such data into a prefetch buffer. ... | 05/23/2006 |
| 7051149 | Method for transceiving non-USB device by an adapter and apparatus using the same A method for transceiving non-USB peripheral device by an adapter and the adapter providing adaptation to an USB interface for the non-USB peripheral device, is disclosed. The adapter can read a capability report from the peripheral device and then converts the capa... | 05/23/2006 |
| 7051148 | Data transmission sequencing method associated with briding device and application system A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as t... | 05/23/2006 |
| 7051145 | Tracking deferred data transfers on a system-interconnect bus Systems and techniques to track deferred data transfers on a system-interconnect bus. A deferral response initiates storage of information corresponding to the response and tracking of progress for a requested data transfer. A master device, such as a bus adapter, m... | 05/23/2006 |
| 7047340 | Databus and method for the communication of two assemblies by means of such a databus A parallel databus assembly and method includes modules connected to parallel signal lines, each of the modules having a databus driver being in immediate connection with the signal lines and a controller connected to the databus driver. At least some of the paralle... | 05/16/2006 |
| 7047374 | Memory read/write reordering Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests... | 05/16/2006 |
| 7047334 | Device for supplying control signals to memory units, and a memory unit adapted thereto A device for supplying control signals to memory units of a memory module comprises a first bus section for supplying a first part of the control signals to a first memory unit. In addition, a second bus section is provided for supplying a second part of the control... | 05/16/2006 |
| 7043612 | Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a second agent on a system bus through a bus bridge so as to maintain ... | 05/09/2006 |
| 7043593 | Apparatus and method for sending in order data and out of order data on a data bus A master unit and a slave unit in a data processor are coupled together by a data bus. The master unit sends data transactions to the slave unit through the data bus and the slave unit executes the data transactions. The present invention comprises an apparatus and ... | 05/09/2006 |
| 7043591 | Cross switch supporting simultaneous data traffic in opposing directions An apparatus comprising a first bus segment, a second bus segment and a switch. The first bus segment may be configured to transfer data in either a first direction or a second direction. The second bus segment may be configured to transfer data in either the first ... | 05/09/2006 |
| 7043568 | Configuration selection for USB device controller A selection system for configuring a device controller. The selection system includes a plurality of state machines each of which has a portion of the configuration information needed to inform a host, connected to the device controller via a serial bus, of the devi... | 05/09/2006 |
| 7039914 | Message processing in network forwarding engine by tracking order of assigned thread in order group A system and method maintains order among a plurality of threads in a multi-threaded processing system. The processing system, which may be disposed at an intermediate network device, has a plurality of processors each supporting a plurality of threads. The ordering... | 05/02/2006 |
| 7039747 | Selective smart discards with prefetchable and controlled-prefetchable address space A bridging device has a first port to allow the device to communicate with other devices on an expansion bus and a second port to allow the device to communicate with devices on a second bus. The device also includes a memory to store data and a processor or logic t... | 05/02/2006 |
| 7035957 | Bus bridge circuit, bus connection system, and buffer control method for bus bridge circuit A PCI bridge circuit connects to first and second PCI buses and performs data transfer between PCI devices. The PCI bridge circuit has a data buffer and controller and the controller 70, prior to the establishment of a data transfer state with the first PCI d... | 04/25/2006 |
| 7035958 | Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in... | 04/25/2006 |
| 7035948 | System and method for USB controllers A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. A... | 04/25/2006 |
| 7032226 | Methods and apparatus for managing a buffer of events in the background A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a n... | 04/18/2006 |
| 7031337 | Data processing apparatus and slave interface mechanism for controlling access to a slave logic unit by a plurality of master logic units The present invention provides a data processing apparatus and slave interface mechanism for controlling access to a slave logic unit by a plurality of master logic units. The data processing apparatus comprises a first bus for coupling a first master logic unit wit... | 04/18/2006 |
| 7028147 | System and method for efficiently and reliably performing write cache mirroring Various embodiments of systems and methods for performing write cache mirroring may involve accessing different mapped regions within a memory. The memory controller may automatically mirror write requests to another memory. Write requests targeting one mapped regio... | 04/11/2006 |
| 7028131 | Reverse message writes and reads A system, method, software and firmware configured to write a message comprising a plurality of words into a memory, such that a last word of the message is written first at a first memory address and a first word of the message is written last at a memory address h... | 04/11/2006 |
| 7028116 | Enhancement of transaction order queue A technique for an enhanced transaction order queue is disclosed. A transaction order queue is used to prioritize transactions flowing through a bridge. The present technique enhances the transaction order queue by providing logic within a module, facilitating the e... | 04/11/2006 |
| 7028111 | Bus system and bus interface for connection to a bus The invention relates to a bus system comprising a first station (202) and a second station (203), (204), coupled by a bus for transferring messages, said bus being designed to operate in accordance with a protocol in which said first station ( | 04/11/2006 |
| 7024533 | Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory contr... | 04/04/2006 |
| 7023801 | Speculative packet selection for transmission of isochronous data A refetch logic propagates data from a first source to a link controller by default. The link controller prefetches data from the refetch logic to generate a first packet prior to receiving control of the transmission medium on which the data is to be transmitted. T... | 04/04/2006 |
| 7020726 | Methods and apparatus for signaling to switch between different bus bandwidths The present invention provides an apparatus and method for selecting bus-width formats. In an exemplary preferred embodiment of the invention, the circuit includes a bus controller configured to provide a first bus-width control signal to select a first bus-width. T... | 03/28/2006 |
| 7016998 | System and method for generating sequences and global interrupts in a cluster of nodes A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigge... | 03/21/2006 |
| 7016994 | Retry mechanism for blocking interfaces An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective request... | 03/21/2006 |
| 7013359 | High speed memory interface system and method The present invention is a high speed serial memory interface system and method that facilitates efficient communication of information between a system controller operating at a relatively high speed serial communication rate and a memory array operating at a relat... | 03/14/2006 |
