Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 7500044 | Digital phase relationship lock loop In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second ... | 03/03/2009 |
| 7487284 | Transaction flow and ordering for a packet processing engine, located within an input-output hub An apparatus and method for controlling data traffic flow and data ordering of packet data between one or more peripheral devices and a processor/memory combination by using a packet processing engine, located within an input-output hub (IOH). The IOH may include a ... | 02/03/2009 |
| 7484029 | Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters A computer-implemented method, apparatus, and computer usable program code are disclosed for migrating a virtual adapter from a source physical adapter to a destination physical adapter in a data processing system where multiple host computer systems share multiple ... | 01/27/2009 |
| 7484030 | Storage controller and methods for using the same In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later ... | 01/27/2009 |
| 7484028 | Burst-capable bus bridges for coupling devices to interface buses Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device. In one aspect, interface buses group the data lines according to gro... | 01/27/2009 |
| 7478189 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 01/13/2009 |
| 7454551 | Reconstructing transaction order using clump tags A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decod... | 11/18/2008 |
| 7447826 | Receive buffer in a data storage system A method according to one embodiment may include receiving data in a receive buffer, the receive buffer comprising a plurality of buffers, and sending a hold command to a transmitting node currently sending data to hold transmission of additional data when a level o... | 11/04/2008 |
| 7444444 | Message processing system and method using external storage The invention relates to a message processing system and method using an external storage medium. Upon receiving a message, the system and method examine the status of a first internal memory. If the first internal memory has an insufficient reserved space, the mess... | 10/28/2008 |
| 7441065 | Method and apparatus for a two-wire serial command bus interface A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol sig... | 10/21/2008 |
| 7424566 | Method, system, and apparatus for dynamic buffer space allocation An interconnect apparatus provides for the buffering of information in respective transaction buffers according to transaction type. An additional buffer is dynamically assignable to one of the transaction buffers where additional capacity is required by that transa... | 09/09/2008 |
| 7424567 | Method, system, and apparatus for a dynamic retry buffer that holds a packet for transmission An interconnect apparatus provides for the buffering of information among a plurality of retry buffers in an output port. An additional buffer is dynamically assignable to one of the N retry buffer means where additional capacity is required by that retry buffer. | 09/09/2008 |
| 7424565 | Method and apparatus for providing efficient output buffering and bus speed matching An interconnect apparatus includes a transaction packet buffer and control logic. The control logic can be operable sequentially to write transaction packets for transmission to the transaction packet buffer and to transmit the buffered transaction packets in sequen... | 09/09/2008 |
| 7421520 | High-speed I/O controller having separate control and data paths An I/O controller having separate command and data paths, thereby eliminating the bandwidth used by the commands and thus increasing bandwidth available to the data buses. Additionally, the I/O controller uses multiple dedicated data paths, for example, dedicated di... | 09/02/2008 |
| 7421522 | Techniques for transmitting and receiving SPI4.2 status signals using a hard intellectual property block Techniques for transmitting and receiving FIFO status signals on a hard intellectual property (HIP) block of a programmable logic integrated circuit are provided. The FIFO status signals are demultiplexed after being received in the HIP block and then stored in a pe... | 09/02/2008 |
| 7418521 | Controller for bridging a host computer and networked laundry machines A laundry system has a plurality of laundry machines networked together and a remotely located host computer for collecting operation data and audit data from the laundry machines and to program the laundry machines with operation parameters. A bridging controller i... | 08/26/2008 |
| 7418537 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 08/26/2008 |
| 7415580 | System for determining the position of an element in memory A system for determining a position of an element in memory comprising a memory queue with a plurality of separate entries and propagate and generate logic in communication with the memory queue such that the propagate and generate logic is operable to inspect each ... | 08/19/2008 |
| 7412555 | Ordering rule and fairness implementation In one embodiment, a controller comprises one or more transaction queues, one or more age counter circuits, and a control circuit. The transaction queues are configured to store a plurality of transaction requests, each having a transaction type. The age counter cir... | 08/12/2008 |
| 7412549 | Processing system and method for communicating data A method for communicating data between an initiator unit (INIT) which initiates the communication and a target unit (TRGT) is described. Therein the initiator unit (INIT) indicates a request (TID) to initiate a communication. In response the target unit (TRGT) prov... | 08/12/2008 |
| 7409476 | System and method for USB controllers A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. A... | 08/05/2008 |
| 7398339 | Method and system for improving the latency in a data transmission system A system for transferring data packets between a data packet transfer core and a number of clients of an application layer, including an interface between the data packet transfer core and the application layer for transferring data packets from the packet transfer ... | 07/08/2008 |
| 7398344 | Plural interfaces in home network with first component having a first host bus width and second component having second bus width Universal network interfaces for a home network connect disparate components to the network, such as relatively complex components (TVs, computers) and relatively simple components (audio boom boxes). ... | 07/08/2008 |
| 7389375 | System, method and storage medium for a multi-mode memory buffer device A multi-mode memory buffer device for use in various memory subsystem structures. The buffer device includes a packetized multi-transfer interface which is redriven to permit connection between a first memory assembly and cascaded memory assemblies. The buffer devic... | 06/17/2008 |
| 7373444 | Systems and methods for manipulating entries in a command buffer using tag information Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the entries can be removed if the corresponding transactions are canceled. In one embodiment, multiple master de... | 05/13/2008 |
| 7373555 | Systems and methods controlling transaction draining for error recovery Disclosed are systems and methods for controlling transaction draining for error recovery comprising asserting a control signal to prevent system resources associated with a particular error from issuing new requests, dropping transactions tracked by an out-of-order... | 05/13/2008 |
| 7373440 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to s... | 05/13/2008 |
| 7370133 | Storage controller and methods for using the same In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later ... | 05/06/2008 |
| 7370171 | Scalable buffer control for a tracing framework A method for storing a tracing event including encountering a tracing probe, selecting a probe buffer corresponding to the tracing probe, obtaining a buffer within the probe buffer using a thread identifier corresponding to a thread that encountered the tracing prob... | 05/06/2008 |
| 7370124 | Method and device for transmitting messages over a data network In a method and system for transmitting messages over a data network, the communication task is used which is implemented on a transmitting microcontroller which determines, on the basis of a routing table, which communication system is used to forward the message t... | 05/06/2008 |
| 7370132 | Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock pow... | 05/06/2008 |
| 7370127 | High-speed internal bus architecture for an integrated circuit An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interf... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370165 | Apparatus and method for protecting data recording on a storage medium A controller for protecting data on a data storage medium is disclosed. A single physical data storage device is divided into a protected data space, a virtual data space and an unprotected data space in an installation mode. Subsequently, the protected and unprotec... | 05/06/2008 |
| 7366872 | Method for addressing configuration registers by scanning for a structure in configuration space and adding a known offset A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure ... | 04/29/2008 |
| 7366817 | Frame order processing apparatus, systems, and methods Apparatus and systems, as well as methods and articles, may bridge between a link layer and a transport layer in a multi-lane serial-attached small computer system interface (SCSI)-serial SCSI protocol (SAS-SSP) device. A lane number first-in first-out buffer (FIFO)... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7366802 | Method in a frame based system for reserving a plurality of buffers based on a selected communication protocol A method according to one embodiment may include reserving a plurality of buffers having an aggregate capacity, receiving a frame having a size less than the aggregate capacity, and releasing at least one of the plurality of buffers that is unused to store the frame... | 04/29/2008 |
| 7366943 | Low-latency synchronous-mode sync buffer circuitry having programmable margin Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference clock signal, marked by the assertion of a periodic sync signal. The ... | 04/29/2008 |
| 7363389 | Apparatus and method for enhanced channel adapter performance through implementation of a completion queue engine and address translation engine A method and apparatus for enhancing channel adapter performance that includes a host interface, a link interface, a packet processing engine, an address translation engine, and a completion queue engine. The host interface is connected to a memory by a local bus. T... | 04/22/2008 |
