Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 6965961 | Queue-based spin lock with timeout A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption... | 11/15/2005 |
| 6963947 | Driver supporting bridge method and apparatus A methodology by which a host computer can dynamically rebalance PCI-to-PCI bridges to overcome Operating System/BIOS and Chipset limitations in order to allow multiple level PCI buses. This methodology also allows hot-swappable PCI buses to be added and removed wit... | 11/08/2005 |
| 6963946 | Descriptor management systems and methods for transferring data between a host and a peripheral An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next location to be written in a queue. The system also allows an incoming des... | 11/08/2005 |
| 6963948 | Microcomputer bridge architecture with an embedded microcontroller An integrated circuit, a computer system, and a method of operating the computer system. The integrated circuit includes an internal bus, a microcontroller connected to the internal bus, an Ethernet controller coupled to the internal bus, and a plurality of buffers ... | 11/08/2005 |
| 6961802 | Data input/output device, memory system, data input/output circuit, and data input/output method When an output of data is switched from a memory to a memory controller, the memory controller takes in write data output from the memory, and outputs the write data taken in to a data bus. Subsequently, the memory controller outputs read data taken thereinto to the... | 11/01/2005 |
| 6961800 | Method for improving processor performance Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before... | 11/01/2005 |
| 6961797 | Computer system using an interfacing circuit to increase general purpose input/output ports According to the claimed invention, the computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, and a south bridge electrically connected to the north bri... | 11/01/2005 |
| 6961837 | Method and apparatus for address translation pre-fetch An end of a queue or a page-crossing within a queue is detected. A virtual memory address for the head of the queue or for the next queue page is pre-translated into a physical memory address while the last entry in the queue or in the current queue page is being se... | 11/01/2005 |
| 6959355 | Universal serial bus hub with shared high speed handler A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ... | 10/25/2005 |
| 6959367 | System having read-modify-write unit A data processing system incorporates a central processing unit to decode and execute given instructions; a memory to store given data; a bus interface unit, provided between the central processing unit and the memory, to start a read bus cycle to read data from the... | 10/25/2005 |
| 6959257 | Apparatus and method to test high speed devices with a low speed tester An apparatus coupled to a low speed tester and a device is disclosed. The device may have a first speed faster than a second speed of the low speed tester. The apparatus may be configured to allow the low speed tester to perform high speed tests of the device at the... | 10/25/2005 |
| 6957293 | Split completion performance of PCI-X bridges based on data transfer amount Embodiments are provided in which a method is described for transferring data in a digital system including a first bus, a second bus, a PCI-X bridge coupling the first and second buses, and a first device and a second device residing on the first and second buses, ... | 10/18/2005 |
| 6957356 | Method and apparatus for iTD scheduling A device is presented including a host controller to generate a transaction schedule. The transaction schedule includes many transactions. The transactions are stored in many data structures. Each of the data structures contain initialized transactions or initialize... | 10/18/2005 |
| 6954820 | Bus bridge including first and second memory areas corresponding to first and second buses A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, ... | 10/11/2005 |
| 6954450 | Method and apparatus to provide data streaming over a network connection in a wireless MAC processor A method of wirelessly transmitting or receiving a packet of information, and an apparatus to wirelessly transmit or receive a packet of information. In the case of transmitting, the method includes streaming a data element, including at least some of the contents o... | 10/11/2005 |
| 6954809 | Apparatus and method for accessing computer system resources via serial bus An apparatus for monitoring the state of computer system resources. According to the invention, the apparatus includes bus interface logic and a queue. The bus interface logic is used to interface with a serial bus and parse a bitstream through the serial bus into a... | 10/11/2005 |
| 6950898 | Data amplifier having reduced data lines and/or higher data rates A data amplifier configured to allow for fewer data lines and/or increased processing speeds. Specifically, multiple helper flip-flops are used to prefetch data in a data amplifier. The helper flip-flops are configured to latch one or two of the data bits from a 4-b... | 09/27/2005 |
| 6950905 | Write posting memory interface with block-based read-ahead mechanism A method may involve: receiving a request to perform a block write to a target device and data associated with the block write; buffering the data associated with the block write prior to completing the block write to the target device; storing an indication identif... | 09/27/2005 |
| 6948081 | Apparatus and method for conserving power in a monitor A power saving apparatus of a monitor which is capable of reducing power consumption in a monitor by controlling the power supplied to a signal sensor in a power saving mode and a controlling method thereof are provided. The power saving apparatus includes a power s... | 09/20/2005 |
| 6944731 | Dynamic random access memory system with bank conflict avoidance feature A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks co... | 09/13/2005 |
| 6941405 | System and method capable of offloading converter/controller-specific tasks to a system microprocessor Systems are provided for the offloading of protocol control and conversion information within microprocessor-based systems. A converter controller comprises a first interface and protocol, as well as a second interface and protocol. An intermediate protocol and inte... | 09/06/2005 |
| 6941407 | Method and apparatus for ordering interconnect transactions in a computer system A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interc... | 09/06/2005 |
| 6941256 | Bus structure, database and method of designing interface With respect to each application, libraries, corresponding to operation models, for describing operations respectively attained by employing a Neumann CPU (bus structure), a Harvard CPU (bus structure) and a direction separate type CPU (bus structure) are registered... | 09/06/2005 |
| 6941408 | Bus interface system with two separate data transfer interfaces The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end devi... | 09/06/2005 |
| 6941364 | Modular-type home gateway system including ADSL controller and homePNA controller A modular-type home gateway system that includes a HomePNA controller connectable to an existing home telephone line, for providing a home network interface; an ADSL controller connected to a prior outdoor telephone line for providing an access network interface; an... | 09/06/2005 |
| 6941424 | System, method, and computer program product for high speed DMA-based backplane messaging A system and method of enhanced backplane messaging among a plurality of computer boards communicating over a common bus uses a set of pre-allocated buffers on each computer board to receive messages from other computer boards. Each sending computer board is represe... | 09/06/2005 |
| 6941393 | Pushback FIFO The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded fro... | 09/06/2005 |
| 6938103 | Universal serial bus transaction processing tasks scheduling method for computer system, involves assigning transaction to periodic queue head list with faster polling interval An apparatus and method is provided for scheduling USB transaction processing tasks. A periodic queue head list associated with a USB host controller is configured to be processed once every polling period. The periodic queue head list describes a location of the US... | 08/30/2005 |
| 6936833 | Semiconductor device package having a switcher connecting plural processing elements A package includes a plurality of processors 101-104 as processing elements. One of the processing elements is selected as a switcher 110 and the switcher is located at the center of the package. Each of the processors 101-104 includes a corresp... | 08/30/2005 |
| 6938106 | Network device interface for digitally interfacing data channels to a controller via a network The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data rec... | 08/30/2005 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing... | 08/23/2005 |
| 6934790 | Data transmitting and receiving system with speedy retransmission of missing data and data receiving device A system for transmitting and receiving data between a data transmitting device such as a computer and a data receiving device such as a peripheral device is capable of shortening the time required to complete transmission and receipt of all of the data, including r... | 08/23/2005 |
| 6934797 | Counter in CAM word A method and apparatus for determining the age and frequency of use of words within a Content Addressable Memory (CAM) is disclosed. The CAM utilizes an aging process which determines the level or frequency of activity on every entry in the database, and purges or i... | 08/23/2005 |
| 6931473 | Data transfer via Host/PCI-X bridges Embodiments are provided in which a method is described for a processor to perform a task of accessing a PCI-X device via a PCI-X bridge, the PCI-X bridge including a processing circuit. The processor builds M read/write control blocks (RWCBs), M being a positive in... | 08/16/2005 |
| 6931472 | Integrated circuit and information processing device In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provi... | 08/16/2005 |
| 6928495 | Method and system for an adaptive multimode media queue Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or ... | 08/09/2005 |
| 6927992 | Trace-impedance matching at junctions of multi-load signal traces to eliminate termination A module board has trace impedances that are matched at trace junctions. An input line that drives a signal to a junction has its impedance adjusted to match the equivalent impedance of branch traces output from the junction. Since input and output impedances match,... | 08/09/2005 |
| 6928528 | Guaranteed data synchronization A method and apparatus for guaranteed data synchronization. In one embodiment, a data synchronization unit includes a memory unit, a write pointer unit, a read pointer unit, and synchronization pulse logic. The memory unit may receive information from a source exter... | 08/09/2005 |
| 6928508 | Method of accessing a remote device from a host by mapping an address of the device to a memory address of the host A protocol for facilitating access to a local input/output device of a remote node across a network. The local input/output device is configured according to a local communication technology (e.g., PCI—Peripheral Component Interconnect), but is accessed remotely (... | 08/09/2005 |
| 6925089 | Mechanism to consolidate HPNA three network states into two network states The present invention provides a network state machine which supports the three network states of the Home Phone Line Networking Alliance specification version 2.0 (HPNA 2.0) using two network states has been disclosed. When a station is in the V1M2 mode, instead of... | 08/02/2005 |
