Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 8352664 | Information processing apparatus including first and second data processors having plural power consumption modes and associated methodology An information processing apparatus including a first data processor processing data sent from an external device, which can switch a power consumption mode thereof; a switcher configured to switch the mode of the first data processing device from the standard power... | 01/08/2013 |
| 8332564 | Data processing apparatus and method for connection to interconnect circuitry A data processing apparatus has a main controller for executing a programmable sequence of instructions including a transaction sequence of instructions used to process a transaction to be initiated by the data processing apparatus. The transaction sequence of instr... | 12/11/2012 |
| 8321618 | Managing conflicts on shared L2 bus One embodiment of the present invention sets forth a mechanism to schedule read data transmissions and write data transmissions to/from a cache to frame buffer logic on the L2 bus. When processing a read or a write command, a scheduling arbiter examines a bus schedu... | 11/27/2012 |
| 8271715 | Modular scalable PCI-Express implementation In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers are accessed by the functional PCI Express port. Other embodiments are described and claimed. ... | 09/18/2012 |
| 8271716 | Virtualization of an input/output device for supporting multiple hosts and functions by using an ingress manager for accepting into a buffer communications identified by functions hosted by a single host Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamical... | 09/18/2012 |
| 8266361 | Access methods and circuits for devices having multiple buffers An integrated circuit device may include a mask register that stores mask values writable from a processor interface; and mask logic that selectively masks status indications from each of a plurality of buffers according to stored mask values; wherein the buffers al... | 09/11/2012 |
| 8261001 | Network range extender device An apparatus includes a PHY assembly in electrical communication with a first interface assembly and with a second interface assembly, the PHY assembly configured to receive a power signal from a PSE, the PHY assembly having a first PHY and a second PHY. The first P... | 09/04/2012 |
| 8166226 | Apparatus and related method for maintaining read caching data of south bridge with north bridge A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically ... | 04/24/2012 |
| 8145822 | Computer system for electronic data processing One aspect relates to a computer system including a first data processing unit, a second data processing unit and a data transmission/memory device. The data transmission/memory can transmit sets of data from the first data processing unit to the second data process... | 03/27/2012 |
| 8131907 | Multi-processor system supporting dynamic power saving and dynamic power saving method thereof A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the ... | 03/06/2012 |
| 8112570 | Pipelined buffer interconnect with trigger core controller A method and system to transfer a data stream from a data source to a data sink are described herein. The system comprises a trigger core, a plurality of dedicated buffers and a plurality of dedicated buses coupled to the plurality of buffers, trigger core, the data... | 02/07/2012 |
| 8090893 | Input output control apparatus with a plurality of ports and single protocol processing circuit The input output control device is provided with a plurality of fiber channel interface circuits and a protocol processing circuit capable of sequentially executing the protocol processing of each port, and is provided with a reception port identification register c... | 01/03/2012 |
| 8090892 | Ordered queue and methods therefor A device receives a first request from a requesting device for first information that is stored at contiguous address locations beginning at a first address. A plurality of spawned requests are generated that each request a different portion of the first information... | 01/03/2012 |
| 8078786 | Method and system for request accessing and scheduling A request scheduling method is provided in a request accessing system having a processing unit, an upstream unit coupled to the processing unit, a downstream unit coupled to the processing unit and the upstream unit, and at least one endpoint device coupled to the u... | 12/13/2011 |
| 8065461 | Capturing read data Various techniques are disclosed for providing data retrieved from a memory device and furnished to a memory bus in response to a read operation to a local bus interface. For instance, a set of conductive traces may be provided that forms a communication path betwee... | 11/22/2011 |
| 8041871 | System and method for providing address decode and virtual function (VF) migration support in a peripheral component interconnect express (PCEI) multi-root input/output virtualization (IOV) environment The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction ... | 10/18/2011 |
| 7970977 | Deadlock-resistant bus bridge with pipeline-restricted address ranges A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address t... | 06/28/2011 |
| 7958298 | System and method for providing address decode and virtual function (VF) migration support in a peripheral component interconnect express (PCIE) multi-root input/output virtualization (IOV) environment The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction ... | 06/07/2011 |
| 7941584 | Data processing apparatus and method for performing hazard detection A data processing apparatus and method are provided for performing hazard detection in a series of access requests issued by processing circuitry for handling by one or more slaves. The requests include one or more write access requests to be performec by an address... | 05/10/2011 |
| 7937519 | Lane merging A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data w... | 05/03/2011 |
| 7937518 | Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters A computer-implemented method, apparatus, and computer usable program code are disclosed for migrating a virtual adapter from a source physical adapter to a destination physical adapter in a data processing system where multiple host computer systems share multiple ... | 05/03/2011 |
| 7895239 | Queue arrays in network devices A queue descriptor including a head pointer pointing to the first element in a queue and a tail pointer pointing to the last element in the queue is stored in memory. In response to a command to perform an enqueue or dequeue operation with respect to the queue, fetc... | 02/22/2011 |
| 7882296 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 02/01/2011 |
| 7822906 | Data flush methods A bridge capable of preventing data inconsistency without degrading system performance is provided, in which a buffering unit comprises a plurality of buffers, a first master device outputs a flush request to flush the buffering unit, and a flush request control cir... | 10/26/2010 |
| 7822905 | Bridges capable of controlling data flushing and methods for flushing data A bridge capable of preventing data inconsistency is provided, in which a first master device outputs a flush request, a buffering unit buffers data or instructions, and a flush request control circuit records a buffer write pointer of the buffer according to the fl... | 10/26/2010 |
| 7822904 | Capturing read data Various techniques for capturing read data from a memory bus are disclosed herein. In one embodiment, a computing system includes a memory device, a memory bus in communication with the memory device, a memory bus interface, a local bus, and a local bus interface. T... | 10/26/2010 |
| 7783817 | Method and apparatus for conditional broadcast of barrier operations A weakly-ordered processing system implements an execution synchronization bus transaction, or “memory barrier” bus transaction, to enforce strongly-ordered data transfer bus transactions. A slave device that ensures global observability may “opt out” of the... | 08/24/2010 |
| 7752375 | Input output control apparatus with a plurality of ports and single protocol processing circuit The input output control device is provided with a plurality of fibre channel interface circuits and a protocol processing circuit capable of sequentially executing the protocol processing of each port, and is provided with a reception port identification register c... | 07/06/2010 |
| 7725640 | Adapter card replay buffer for system fault analysis An adapter card for directing an information handling system (or another device) device to copy one or more data packets buffered in its memory may include an interface core. The interface core may comprise an electric circuit including electronic components and con... | 05/25/2010 |
| 7707346 | PCI express multi-root IOV endpoint retry buffer controller The link layer of the multi-root PCI (peripheral component interconnect) express device stores transaction layer packets (TLPs) sent from a transaction layer in a dedicated retry buffer dedicated to the virtual hierarchy (VH) associated with the TLP. The link layer ... | 04/27/2010 |
| 7702841 | Semiconductor integrated circuit and image processing apparatus having the same An ASIC includes a receiving unit, a transmission interface, a reception interface, a buffer, and a control unit. When the receiving unit receives a second write request while the transmission interface is in process of transmitting to a transmission line a first wr... | 04/20/2010 |
| 7694061 | Discarding a partially received message from a data queue Devices in a process control system communicate by data messages over a communication medium segment. Each device includes a communication controller that includes a received data memory and a plurality of received message objects. When a message is received, a rece... | 04/06/2010 |
| 7685351 | External device access apparatus In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master,... | 03/23/2010 |
| 7685352 | System and method for loose ordering write completion for PCI express A method for managing the protocol of read/write messages in a PCI Express communication link is disclosed. The method comprises maintaining queues of write requests and read requests associated with each of a plurality of request identifications that are contained ... | 03/23/2010 |
| 7669000 | Host bus adapter with multiple hosts A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each h... | 02/23/2010 |
| 7660933 | Memory and I/O bridge The present invention is directed to an improved memory and I/O bridge that provides an improved interface for communicating data between the data bus of the system processor and the memory controller. The memory and I/O bus bridge according to the present invention... | 02/09/2010 |
| 7657689 | Methods and apparatus for handling reset events in a bus bridge Methods and apparatus are provided for handling reset events in a bus bridge. A system on a programmable chip includes master components and slave components supporting various bus protocols. Bus bridges allow components using different bus protocols to interact. Re... | 02/02/2010 |
| 7657690 | Control of PCI memory read behavior using memory read alias and memory command reissue bits A method of controlling memory read behavior in PCI devices includes connecting a master PCI device to a PCI bus. The master PCI device is constructed and arranged to issue a Memory Read Line or a Memory Read Multiple initial command. A target PCI bridge device is c... | 02/02/2010 |
| 7634610 | Reconstructing transaction order using clump tags A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decod... | 12/15/2009 |
| 7624221 | Control device for data stream optimizations in a link interface Optimization logic that optimizes a stream of requests being transmitted onto a link by a link interface unit can be enabled or disabled based on a performance metric that represents a measure of the degree to which a response to a request is likely to be slowed due... | 11/24/2009 |
