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| Number | Title | Issue Date |
| 6003104 | High speed modular internal microprocessor bus system A CPU of a microprocessor includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU has a plurality of first ports coupled to respective first ports of the module units via dedicated buses therebetween and has a second po... | 12/14/1999 |
| 5987558 | Method and apparatus for resolving over lapping selection and reselection operations of SCSI bus protocols A SCSI bus extender apparatus coupling a primary SCSI bus to a secondary SCSI bus includes a mechanism for detecting and resolving contention between a substantially simultaneous SELECTION operation on the primary bus and a RESELECTION operation on the se... | 11/16/1999 |
| 5970234 | PCI bus arbiter and a bus control system having the same A PCI bus arbiter is provided as an additional PCI bus in PCI peer-to-peer bus bridge system. A bus control system having the PCI bus arbiter is also provided. The bus control system includes bus masters, a first PCI bus bridge, a second PCI bus bridge, a... | 10/19/1999 |
| 5951667 | Method and apparatus for connecting expansion buses to a peripheral component interconnect bus Modern personal computers often have several internal buses. An integrated expansion bus bridge is disclosed that couples to a fast main computer bus and couples several different expansion buses to the fast main computer bus. In one personal computer emb... | 09/14/1999 |
| 5951668 | Method and system for transferring data between buses having differing ordering policies A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data on a second bus h... | 09/14/1999 |
| 5930485 | Deadlock avoidance in a computer system having unordered slaves A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementati... | 07/27/1999 |
| 5878237 | Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of peripheral component interconnect ("PCI") buses capable of operating at 66 MHz. Each of the plurality of PCI buses have the same logica... | 03/02/1999 |
| 5875310 | Secondary I/O bus with expanded slot capacity and hot plugging capability A computer system is provided which supports an increase in the number of pluggable cards on the secondary I/O bus by using driver/receiver modules and direction control logic in place of more complex and more expensive bus to bus bridges. The number of p... | 02/23/1999 |
| 5872941 | Providing data from a bridge to a requesting device while the bridge is receiving the data A computer system includes a data storage device on a first data bus, a requesting device that initiates a delayed request on a second data bus, and a bridge device that delivers the delayed request to the first data bus and, after the requesting device r... | 02/16/1999 |
| 5864686 | Method for dynamic address coding for memory mapped commands directed to a system bus and/or secondary bused In a data processing system including a system bus supporting memory mapped devices, dynamic response to a memory mapped command is achieved by receiving a status response from each device attached to the system bus and comparing a priority associated wit... | 01/26/1999 |
| 5857087 | Method of handshaking in a data communications bus A pipelined bus which can support more than one channel between data sources and data destinations at a time. The bus includes an arbitration bus, a command bus and a data bus. In accordance with the bus protocol, different channels may access the various... | 01/05/1999 |
| 5835739 | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests or... | 11/10/1998 |
| 5822549 | Computer system and bus controller for controlling access to a computer bus A bus controller controls access to a computer bus by a plurality of bus requesters. The bus controller activates a priority bus request line on the computer bus regardless of which of plural priority bus agents desires to transmit a transaction on the co... | 10/13/1998 |
| 5815674 | Method and system for interfacing a plurality of bus requesters with a computer bus A bus controller controls access to a processor bus by arbitrating between bus requests received from a plurality of bus requesters. The bus controller employs a pipelining arbitration mechanism in which a first bus requests from each bus requester is buf... | 09/29/1998 |
| 5805844 | Control circuit for an interface between a PCI bus and a module bus A control circuit for the interface circuit of a module of a distributed process control system permits its kernel submodule and peripheral submodule to communicate through the interface circuit notwithstanding that the structure and protocol of module BU... | 09/08/1998 |
| 5793992 | Method and apparatus for arbitrating access to main memory of a computer system A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data... | 08/11/1998 |
| 5790815 | Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent byte slicing A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time... | 08/04/1998 |
| 5781187 | Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously ... | 07/14/1998 |
| 5778235 | Computer system and arbitrator utilizing a bus bridge that avoids livelock A computer system and arbitrator prevent a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1... | 07/07/1998 |
| 5761455 | Dynamic bus reconfiguration logic A parallel processing system is provided with a plurality of processors and a plurality of memories, and bus units with arbitration coupling the processors and memories. A bus unit provides a pathway between one processor and the bus unit's respective mem... | 06/02/1998 |
| 5758109 | Repeater/switch for distributed arbitration digital data buses The technical field of the invention generally concerns digital computers and, in particular, repeaters or switches (40) for distributed arbitration digital data buses (52, 54, 56, and 58) to which devices (62, 64, 66, 68, 72 and 74) connect in parallel. ... | 05/26/1998 |
| 5754801 | Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent data transfers A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time... | 05/19/1998 |
| 5748921 | Computer system including a plurality of multimedia devices each having a high-speed memory data channel for accessing system memory A computer system including a plurality of multimedia devices each having a high-speed memory data channel for accessing system memory. Each multimedia device has a high speed link directly to system memory, which is preferably single or multiple ported m... | 05/05/1998 |
| 5734846 | Method for avoiding livelock on bus bridge A method prevents a livelock condition from occurring between a host bus bridge (e.g., memory controller) and a PCI bus bridge, where the host bus bridge and PCI bus bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Spec... | 03/31/1998 |
| 5717876 | Method for avoiding livelock on bus bridge receiving multiple requests A method prevents a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Sp... | 02/10/1998 |
| 5684966 | Method for operating a repeater for distributed arbitration digital data buses The technical field of the invention generally concerns digital computers and, in particular, repeaters or switches (40) for distributed arbitration digital data buses (52, 54, 56, and 58) to which devices (62, 64, 66, 68, 72 and 74) connect in parallel. ... | 11/04/1997 |
| 5675750 | Interface having a bus master arbitrator for arbitrating occupation and release of a common bus between a host processor and a graphics system processor An interface for a high-performance graphics adapter is provided. In a computer system which includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application comp... | 10/07/1997 |
| 5649209 | Bus coupling information processing system for multiple access to system bus When a first bus master device issues a bus request on a first request signal line, a centralized arbitration circuit in a system bus manage circuit issues a bus grant signal on a first grant signal line if the bus is available for use. This causes the fi... | 07/15/1997 |
| 5644733 | Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses Two partitioned systems are interconnected by bus exchange modules which connect to first and second system common busses. Each system common bus shares three or more requestors, and an arbitration logic unit in each partition manages bus access priority ... | 07/01/1997 |
| 5640520 | Mechanism for supporting out-of-order service of bus requests with in-order only requesters devices An arbiter for the local bus of a computer system. The system contains a bridge and a plurality of agent devices that are all connected to a local bus. The bridge links the local system to a remote system. The bridge and one of the agents (DEFER agent) wi... | 06/17/1997 |
| 5630078 | Personal computer with processor reset control This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system h... | 05/13/1997 |
| 5627976 | Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bu... | 05/06/1997 |
| 5619726 | Apparatus and method for performing arbitration and data transfer over multiple buses An apparatus and method for arbitrating bus ownership of a first communication bus ("C1-bus") for a plurality of C1-bus masters and arbitrating bus ownership of a second communication bus ("C2-bus") for a plurality of C2-bus masters. The apparatus further... | 04/08/1997 |
| 5619661 | Dynamic arbitration system and method A dynamic arbitration system for controlling the data transfer between primary and secondary buses in a personal computer has master and target components on both buses. Primary and secondary bus arbiters are included in a bridge circuit, and initially op... | 04/08/1997 |
| 5606673 | Small computer system interface (SCSI) controller Where a command having a selection waiting phase unifies standard operations to take place in different SCSI phases, if an SCSI controller is selected before the command is issued, the command issued will be disregarded. The problem of the command being d... | 02/25/1997 |
| 5596729 | First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, a... | 01/21/1997 |
| 5586265 | Priority arbitrating interface for a plurality of shared subsystems coupled to a plurality of system processing devices for selective association of subsystem to processing device The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to a control circuit. The control circuit is comprised of a programmable microprocessor in bus communication w... | 12/17/1996 |
| 5579486 | Communication node with a first bus configuration for arbitration and a second bus configuration for data transfer A node for a communication system that has a plurality of nodes, each of which may be coupled to a local host. The nodes are coupled between themselves in a tree topology by a plurality of point-to-point links. The interconnected nodes provide a first bus... | 11/26/1996 |
| 5577230 | Apparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetch This arbitration unit includes a request controller and two bus controllers. The request controller monitors the instruction fetch or data requests and causes the two bus controllers to implement an instruction fetch or data transfer through one of the tw... | 11/19/1996 |
| 5566306 | Transfer control apparatus for independent transfer of data from a storage device to an I/O device over a secondary bus A data transfer control apparatus capable of continuously transferring large amounts of data without decreasing the performance of a system CPU. The data transfer control apparatus uses one or more external storage device interfaces to control transfer of... | 10/15/1996 |
