Quotables
"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5557754 | Computer system and system expansion unit To enable a computer system such that each local arbiter is supposed to output its own priority as the right to use the bus on a common arbitration bus through open-collector-type drivers to determine a winner in arbitration, to expand the bus by way of a... | 09/17/1996 |
| 5555383 | Peripheral component interconnect bus system having latency and shadow timers A PCI system is provided with a shadow register and a shadow timer. When a master device sends an address designating a target device that is connected to another bus, the device's latency value is recorded in the shadow register. While the PCI-PCI bridge... | 09/10/1996 |
| 5517650 | Bridge for a power managed computer system with multiple buses and system arbitration A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. Devices coupled to the buses are either PCI bus-compliant d... | 05/14/1996 |
| 5481681 | Data transfer operations between two asynchronous buses A technique for permitting data transfers between a high speed bus and a low speed bus which operate independently and asynchronously wherein when the low speed bus requires access to the high speed bus, the busy status of the latter bus is determined and... | 01/02/1996 |
| 5463740 | Data control device generating different types of bus requests and transmitting requests directly to one of a number of arbiters for obtaining access to a respective bus A data control device which acquires the right to use a bus and performs data control includes a request circuit which selectively generates a plurality of request signals for acquiring the right to use corresponding buses. The plurality of request signal... | 10/31/1995 |
| 5450551 | System direct memory access (DMA) support logic for PCI based computer system A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge ... | 09/12/1995 |
| 5418914 | Retry scheme for controlling transactions between two busses A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when ... | 05/23/1995 |
| 5369748 | Bus arbitration in a dual-bus architecture where one bus has relatively high latency A dual-bus architecture that includes a high-seed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus... | 11/29/1994 |
| 5353417 | Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are var... | 10/04/1994 |
| 5195089 | Apparatus and method for a synchronous, high speed, packet-switched bus A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of... | 03/16/1993 |
| 5191656 | Method and apparatus for shared use of a multiplexed address/data signal bus by multiple bus masters A multiplexed address/data signal bus capable of supporting multiple bus masters includes a group of control signal lines "shared" by each bus requestor device (BRD) coupled to the bus and a group of control signal lines "replicated" into sets, one for ea... | 03/02/1993 |
| 4958271 | Transfer control equipment A system comprising a plurality of common bus systems, each of which has a given priority of use for peripheral units, and a unique transfer unit. When data is transferred from a unit of one of the common bus systems to a unit of another common bus system... | 09/18/1990 |
| 4422142 | System for controlling a plurality of microprocessors A system for controlling a plurality of microprocessors, comprising a common memory which can be selectively switched to exclusive buses which are connected to the plurality of microprocessors, respectively, and a priority control circuit which determines... | 12/20/1983 |
