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| Number | Title | Issue Date |
| 8122177 | Direct memory access technique for use with PCIe endpoints An integrated circuit (“IC”) includes a peripheral component interconnect express (“PCIe”) root complex having a central processing unit (“CPU”), a memory controller configured to control a main memory of a PCIe system, and a PCIe port coupled to a PCIe ... | 02/21/2012 |
| 8108583 | Direct memory access controller system with message-based programming A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the se... | 01/31/2012 |
| 8037229 | Combination non-volatile memory and input-output card with direct memory access A removable electronic circuit card having both a memory module with a non-volatile mass storage memory and a separate input-output module so that data transfers may be made through the input-output module directly to and from the mass storage memory in a direct mem... | 10/11/2011 |
| 7975090 | Method for efficient I/O controller processor interconnect coupling supporting push-pull DMA read operations A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interc... | 07/05/2011 |
| 7870323 | Bridge circuit for interfacing processor to main memory and peripherals A bridge circuit includes a bus, a memory interface module, a memory control module, and an external storage control module. The memory interface module receives a memory address from a processor via a memory interface and outputs the memory address to the bus. The ... | 01/11/2011 |
| 7865653 | Universal serial bus host controller and control methods thereof The present invention provides a USB host controller and control method thereof. The USB host controller comprises a first controller, a second controller and a first memory. The first controller controls first transfer between a host and a USB device. The second co... | 01/04/2011 |
| 7822903 | Single bus command having transfer information for transferring data in a processing system A processing system and method for transferring data in a processing system. The processing system includes a bus mastering device, a plurality of slave devices, and a bus interconnect configured to switch the bus mastering device between the slave devices. Each of ... | 10/26/2010 |
| 7779194 | Data modification module The present invention relates to a microcontroller including a central processing unit, at least one memory, a bus coupling the storage location to the central processing unit, and a data modification module for modifying data in the at least one memory. The data mo... | 08/17/2010 |
| 7752374 | Method and apparatus for host messaging unit for peripheral component interconnect busmaster devices Peripheral Component Interconnect (PCI) device contains Host Messaging Unit (HMU) which is operative to off load host processor and PCI device processor from PCI bus transfer overhead. HMU is configurable to asynchronously retrieve host processor commands from circu... | 07/06/2010 |
| 7673091 | Method to hide or reduce access latency of a slow peripheral in a pipelined direct memory access system A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a w... | 03/02/2010 |
| 7606961 | Computer system and data pre-fetching method A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a processor core, local memory and DMA module. The local memory of the idlin... | 10/20/2009 |
| 7594057 | Method and system for processing DMA requests Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and i... | 09/22/2009 |
| 7475182 | System-on-a-chip mixed bus architecture A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bri... | 01/06/2009 |
| 7444435 | Non-fenced list DMA command mechanism A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one process... | 10/28/2008 |
| 7444442 | Data packing in a 32-bit DMA architecture A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packin... | 10/28/2008 |
| 7433977 | DMAC to handle transfers of unknown lengths A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the tra... | 10/07/2008 |
| 7424561 | Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second... | 09/09/2008 |
| 7373440 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to s... | 05/13/2008 |
| 7372293 | Polarity driven dynamic on-die termination Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pi... | 05/13/2008 |
| 7373437 | Multi-channel DMA with shared FIFO A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (... | 05/13/2008 |
| 7369131 | Multi-display system and method thereof A multi-display system and a method thereof which solves an overloading problem on a memory bus. The multi-display system includes displays which independently display separate images, a main memory which stores input image signals, image signal process units which ... | 05/06/2008 |
| 7369815 | Power collapse for a wireless terminal An integrated circuit for a modem processor includes processing units that are partitioned into “always-on” and “collapsible” power domains. An always-on power domain is powered on at all times. A collapsible power domain can be powered off if the processing... | 05/06/2008 |
| 7370133 | Storage controller and methods for using the same In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later ... | 05/06/2008 |
| 7363396 | Supercharge message exchanger A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM... | 04/22/2008 |
| 7350014 | Connecting peer endpoints In one embodiment, the present invention includes a method for sending a connection request from a requestor endpoint to a target endpoint based on route information stored in the requestor endpoint, and receiving a connection confirmation from the target endpoint t... | 03/25/2008 |
| 7350012 | Method and system for providing fault tolerance in a network A configurable switching fabric port is disclosed having, in a particular configuration. A first interface that employs port interface resources and leaves at least one interface resource dormant and a second interface utilizing the dormant resource. One particular ... | 03/25/2008 |
| 7350015 | Data transmission device A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it has connections for connecting at least two data buses and can output d... | 03/25/2008 |
| 7349999 | Method, system, and program for managing data read operations on network controller with offloading functions Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target dat... | 03/25/2008 |
| 7342411 | Dynamic on-die termination launch latency reduction Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination... | 03/11/2008 |
| 7343434 | Buffer management within SLS (simple load store) apertures for inter-endpoint communication in advanced switching fabric A single copy memory sharing scheme between multiple endpoints in an interconnect architecture may use a buffer management method in an advanced switching fabric having multiple endpoints that divides a simple load and store memory aperture into a buffer descriptor ... | 03/11/2008 |
| 7340548 | On-chip bus This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting the multiple outstandi... | 03/04/2008 |
| 7340554 | USB host controller with DMA capability An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and... | 03/04/2008 |
| 7340550 | USB schedule prefetcher for low power A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main me... | 03/04/2008 |
| 7337255 | Distributed data handling and processing resources system The distributed data handling and processing resources system of the present invention includes a) a number of data handling and processing resource nodes that collectively perform a desired data handling and processing function, each data handling and processing re... | 02/26/2008 |
| 7330904 | Communication of control information and data in client/server systems The invention provides a method and system in which a client/server system uses a NUMA communication link, possibly in combination with a byte serial communication link, to transfer relatively large blocks of data between client and server. The method and system pro... | 02/12/2008 |
| 7328300 | Method and system for keeping two independent busses coherent Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and th... | 02/05/2008 |
| 7313641 | Inter-processor communication system for communication between processors A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a pr... | 12/25/2007 |
| 7308557 | Method and apparatus for invalidating entries within a translation control entry (TCE) cache A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recent... | 12/11/2007 |
| 7289386 | Memory module decoder A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of mem... | 10/30/2007 |
| 7290069 | Data acquisition system which monitors progress of data storage A pattern may be written to an allocated section of host memory to track how much data has been received in the host memory from a direct memory access controller coupled to a First In, First Out memory. A driver may send the most recently written sample of data fro... | 10/30/2007 |
