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| Number | Title | Issue Date |
| 7165136 | System and method for managing bus numbering Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active... | 01/16/2007 |
| 7165126 | Direct memory access device A direct memory access device is provided which includes: a designation unit for designating transfer modes, when receiving an instruction to transfer data, to perform byte transfers or word transfers for first and last data of the data and word transfers for all ot... | 01/16/2007 |
| 7164689 | Multi-initiator control unit and method The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circu... | 01/16/2007 |
| 7165131 | Separating transactions into different virtual channels In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming tran... | 01/16/2007 |
| 7162003 | Method and apparatus for driving multiple peripherals with different clock frequencies in an integrated circuit The invention is a system for selecting a peripheral, the peripheral receiving a first clock frequency. The invention comprises the following. A processing circuit receives a second clock frequency, where the first and second clock frequencies are different. The pro... | 01/09/2007 |
| 7162563 | Semiconductor integrated circuit having changeable bus width of external data signal A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal add... | 01/09/2007 |
| 7162565 | Universal serial bus interface to mass storage device An improved bridge circuit for connecting a disk drive with an ATA interface to a computer via a USB bus. After the bridge receives the first data from the ATA interface, the bridge makes the assumption that the next read command will probably be for the next sequen... | 01/09/2007 |
| 7162567 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 01/09/2007 |
| 7162566 | USB-based host-to-host networking method The present invention relates to a USB-based host-to-host networking method capable of transferring information between two hosts. Devices for the method comprise: a register, a pair of FIFO control command transmitters and at least one FIFO bulk transmitter. | 01/09/2007 |
| 7162654 | Isolation of I2C buses in a multiple power domain environment using switches A disk enclosure includes a first enclosure controller powered by a first voltage circuit and coupled to a first I2C bus, a second enclosure controller powered by a second voltage circuit and coupled to a second I2C bus, and a switch coupled between the first and th... | 01/09/2007 |
| 7159065 | Method for issuing vendor specific requests for accessing ASIC configuration and descriptor memory while still using a mass storage class driver A bridge-chip may interface a Universal Serial Bus to a mass storage device. Communications of the universal serial bus may be examined to determine a command block wrapper (CBW) of a bulk transport protocol and if a configuration command block (CFGCB) of the CBW ma... | 01/02/2007 |
| 7158536 | Adaptive-allocation of I/O bandwidth using a configurable interconnect topology Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, ... | 01/02/2007 |
| 7159063 | Method and apparatus for hot-swapping a hard disk drive Methods and apparatus are provided for hot swapping a hard disk drive. A gateway is connected between the disk drive and the bus leading to the host adapter. The gateway can isolate the disk drive from the bus prior to a disk drive being removed and can signal to th... | 01/02/2007 |
| 7155553 | PCI express to PCI translation bridge A PCI Express to PCI bridge enables upstream and downstream isochronous data transfer by modifying the PCI bus arbiter so that the PCI device on the PCI bus is treated as a virtual port for the bridge. Data from the PCI device is assigned via a port arbitration tabl... | 12/26/2006 |
| 7155556 | Devices and methods for converting remote device formats to host device formats for access to host associated resources A host integrated circuit device can include a host interface circuit that is configured to access a resource associated with the host integrated circuit device in a first device interface format based on a request from a remote integrated circuit device located out... | 12/26/2006 |
| 7155552 | Apparatus and method for highly available module insertion Modules coupled to multiple connectors can check to see if full connectivity is provided through the connectors. If it is not, for instance because the connectors are mis-seated, the modules can prevent themselves from fully powering up. In a storage environment, a ... | 12/26/2006 |
| 7155549 | VMEbus split-read transaction A method of performing a VMEbus split-read transaction (401) includes providing a master VMEbus module (102) coupled to a slave VMEbus module (104) through a VMEbus network (106). The master VMEbus module initiates a VMEbus split-read tra... | 12/26/2006 |
| 7155525 | Transaction management in systems having multiple multi-processor clusters A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exce... | 12/26/2006 |
| 7155537 | Infiniband isolation bridge merged with architecture of an infiniband translation bridge A method and system for facilitating communication between computer subnets are provided. One embodiment of the present invention comprises presetting buffers in an internal subnet, wherein the buffers help route external commands to a plurality of devices within th... | 12/26/2006 |
| 7152110 | Information exchange between non-networked devices through an intermediary device via a piconet Information exchange among non-networked devices is disclosed. The information exchange occurs through instantaneous networks, like piconets, established between the non-networked devices and an intermediary device. For example, the intermediary device receives info... | 12/19/2006 |
| 7152129 | Apparatus having an inter-module data transfer confirming function, storage controlling apparatus, and interface module for the apparatus In a storage controlling apparatus controlling an access from a host to a disk apparatus, for example, when a data transfer confirmation flag set in a data transfer descriptor is “ON”, a data transfer confirmation descriptor is automatically generated on the bas... | 12/19/2006 |
| 7152130 | Bus system for use with information processing apparatus A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection control... | 12/19/2006 |
| 7152134 | Interfacing a legacy data bus with a wideband data bus utilizing an embedded bus controller Various methods and systems provide interfaces between legacy data buses such as MIL-STD 1553 buses and wideband data buses such as IEEE 1394 data buses. One technique for interfacing a legacy bus to a wideband data bus involves providing a hybrid bus controller/rem... | 12/19/2006 |
| 7152137 | Method for exchanging data between a plurality of subscribers by means of a data bus The invention relates to a method for exchanging data between a plurality of subscribers (K1, K2, K3, K) by means of a data bus. The subscribers are located in their totality in at least two spatially and physically separate subordinate data bus... | 12/19/2006 |
| 7152190 | USB OTG intelligent hub/router for debugging USB OTG devices An apparatus, architecture and method for enabling the debugging of USB OTG devices under development is provided herein. An intelligent router (100) provides the capability to connect to a USB Dual Role Device (DRD) (102) under development, and obtain... | 12/19/2006 |
| 7152133 | Expanded functionality protocol adapter for in-vehicle networks The invention is an improved protocol adapter for in-vehicle networks for diagnostics, analysis and monitoring. The invention has a pass through feature (voltage translator)/smart mode that allows the protocol adapter to emulate older boxes. Visual indicators (LEDs)... | 12/19/2006 |
| 7149874 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 12/12/2006 |
| 7149927 | Use of SMBus to provide JTAG support An emulator is provided on an electronic assembly that permits external logic to communicate with test logic on the electronic assembly over an electrical interface that has fewer signals than the electrical interface associated with the test logic itself. In this w... | 12/12/2006 |
| 7149840 | Universal serial bus interface to mass storage device using speculative write commands An improved USB to ATA bridge circuit that issues a speculative write command upon the completion of an actual write command: The speculative write command assumes that the next write command will write data in a the next sequential data location to that in which da... | 12/12/2006 |
| 7149848 | Computer system cache controller and methods of operation of a cache controller In at least some embodiments, a computer system comprises a central processing unit (“CPU”), a bridge device coupled to a main memory, and a cache controller coupled between the bridge device and the CPU. The computer system further comprises a cache memory coup... | 12/12/2006 |
| 7149786 | Network for data transmission Novel configuration preventing collision of data transmissions on data transmission paths. Repeated transmission attempts after said collisions thus become unnecessary. Transmission capacity of the data network can be used optimally resulting in considerably faster ... | 12/12/2006 |
| 7149823 | System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a prefe... | 12/12/2006 |
| 7149838 | Method and apparatus for configuring multiple segment wired-AND bus systems A special bus master, called a configuration host, “walks” a bus system to discover the bus topology and bus bridges that form that topology. Once the bridges have been located, the configuration host assigns a bridge ID to each bridge and enters information int... | 12/12/2006 |
| 7146459 | Writing a sequence of M bytes to a disk with continuous write steps aligned on 8 byte boundaries A method of writing data to a disk, said method performing a write-modify-read for every partial 8 byte write, said method comprising: receiving a request for a sequence of L bytes; determining whether the last byte of the sequence of L bytes is last byte of an 8 by... | 12/05/2006 |
| 7146452 | Multi-port system and method for routing a data element within an interconnection fabric The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host ... | 12/05/2006 |
| 7145872 | Method for managing system resources in network system in which digital interface is used for connection A method for managing system resources in a network system in which a digital interface is used for connection is provided. The method for managing system resources required for communication between a source device and a sink device includes the steps of (a) initia... | 12/05/2006 |
| 7145921 | Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure An asynchronous data pipe (ADP) automatically generates transactions necessary to complete asynchronous data transfer operations for an application over a bus structure. The ADP includes a register file which is programmed and initiated by the application. The regis... | 12/05/2006 |
| 7146448 | Apparatus and method for adopting an orphan I/O port in a redundant storage controller A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two of the FRUs have microprocessors and memory for processing I/O reque... | 12/05/2006 |
| 7146450 | Control and supervisory signal transmission system for changing a duty factor of a control signal A parent station output section changes a duty factor between a period in which a control data signal is at a level (high-potential low-level) lower than a power supply voltage Vx but higher than high-level signal in other circuit portions and a subsequent period in... | 12/05/2006 |
| 7143227 | Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write command on a first PCI-X bus on one side of the bridge. The target is c... | 11/28/2006 |
