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| Number | Title | Issue Date |
| 4937785 | Visual signal processing backplane bus A custom bus for a visual signal (image) processing system which can interface with a standard high speed industrial standard computer bus and requires minimal interface circuitry. Eight lines are dedicated to eight data/address bits which are supplied to... | 06/26/1990 |
| 4864496 | Bus adapter module for interconnecting busses in a multibus computer system A control adapter module in a bus adapter connecting a high-speed pended bus to a slower speed non-pended bus functions as a node of the non-pended bus. An interconnect bus extends between the control module and a response adapter module functioning as a ... | 09/05/1989 |
| 4695952 | Dual redundant bus interface circuit architecture An asynchronous bus interface circuit manages the transfer of messages between a host processor memory, and one of two redundant serial data buses by separately processing command words thereby permitting efficient handling of status and data words.... | 09/22/1987 |
| 4675803 | System for processing information A system is provided to receive and process information including a processor, an operator station and an interconnect processor. The interconnect processor is coupled to the processor by a first bus, and the interconnect processor is coupled to the opera... | 06/23/1987 |
| 4570220 | High speed parallel bus and data transfer method A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconne... | 02/11/1986 |
| 4476524 | Page storage control methods and means The embodiment provides an independent data bus path between a random access page storage (PS), and a main storage (MS), wherein this independent data bus does not pass through any channel processor (CH) or central processor (CP). Page data transfers on t... | 10/09/1984 |
| 4470113 | Information processing unit An information processing unit, such as a central processor, microprocessor or one-chip microcomputer, which can be used as either a master unit or a slave unit yet does not require the provision of extra external terminals for control signals. The unit i... | 09/04/1984 |
| 4384322 | Asynchronous multi-communication bus sequence An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication busses in a data processing system, wherein the plural commu... | 05/17/1983 |
| 4384327 | Intersystem cycle control logic A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein information may be transferred between plural communication buss... | 05/17/1983 |
| 4300194 | Data processing system having multiple common buses Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the multiple common buses to one of the units in response to bus req... | 11/10/1981 |
| 4296469 | Execution unit for data processor using segmented bus structure A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to occur simultaneously. The circuit is designed to interfac... | 10/20/1981 |
| 4234919 | Intersystem communication link A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory r... | 11/18/1980 |
| 4205373 | System and method for accessing memory connected to different bus and requesting subsystem A method and system for accessing a memory subsystem from a requesting subsystem connected to a first bus. The memory subsystem is connected to a second bus. A pair of adaptors coupled to each other by a cable are respectively connected to the first and s... | 05/27/1980 |
| 4047162 | Interface circuit for communicating between two data highways An interface circuit for use in a data transmission system is designed to be used not only between a highway and a device but also to link highways and can be commanded to enter a status in which commands sent to it on one highway are modified and sent ou... | 09/06/1977 |
| 4041472 | Data processing internal communications system having plural time-shared intercommunication buses and inter-bus communication means A memory subsystem is connected to an addressable port on one bus and a non-memory subsystem is connected to an addressable port on another bus. Access to the memory is achieved by the non-memory subsystem by generating a message having a destination code... | 08/09/1977 |
| 4016546 | Bus switch coupling for series-coupled address bus sections in a microprocessor A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the mic... | 04/05/1977 |
