Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 7594056 | Bridge and data processing method therefor There is provided a bridge which connects between a primary bus and secondary bus. The bridge reads out a descriptor from a primary memory of the primary bus, reads out a status from a secondary memory of the secondary bus, writes, into the primary memory of the pri... | 09/22/2009 |
| 7577781 | Bus system for use with information processing apparatus A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection control... | 08/18/2009 |
| 7574549 | Bridge design for SD and MMC multiplexing A method for determining direction of signal transmission in a bi-directional signal line, including sampling data signals at two terminals, A and B, enabling data flow from A to B when data flow from B to A is not enabled, and a logical 0 bit is sampled at A, enabl... | 08/11/2009 |
| 7543101 | System of accessing data in a graphics system and method thereof A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces ... | 06/02/2009 |
| 7536494 | Expandable slave device system with buffered subsystems A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signal... | 05/19/2009 |
| 7519758 | Method and apparatus for transmitting measurement data between an object detection device and an evaluation device An apparatus and a method for transmitting measurement data between an object-detection device and an evaluation device are provided, the evaluation device sending to the object-detection device one or more data packets with the object identifiers relevant for the e... | 04/14/2009 |
| 7500042 | Access control device for bus bridge circuit and method for controlling the same An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an address corresponding to an access request to the second bus sent fro... | 03/03/2009 |
| 7487283 | Apparatus for bridging two or more data communications interfaces An apparatus is provided for bridging two or more data communications interfaces. The apparatus includes a powered enclosure for receiving and powering one or more storage devices and one or more computing devices and provides a first data communications interface c... | 02/03/2009 |
| 7454550 | Systems and methods for providing co-processors to computing systems Computing systems with conventional CPUs coupled to co-processors or accelerators implemented in FPGAs (Field Programmable Gate Arrays). One embodiment of the systems and methods according to the invention includes a FPGA accelerator implemented in a computer system... | 11/18/2008 |
| 7430252 | Apparatus and method for WGIO phase modulation An apparatus and method for WGIO phase modulation are described. In one embodiment, the method includes the receipt of a high-speed data stream, encoded according to an 8b/10b code. Once received, a symbol rate of the data stream is reduced by a predet... | 09/30/2008 |
| 7428601 | Semiconductor integrated circuit A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the bus line, and a control circuit which is formed at the peripheral circuits. The contr... | 09/23/2008 |
| 7426587 | Semiconductor integrated circuit A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The contro... | 09/16/2008 |
| 7424580 | Data transfer control device, electronic instrument, program and method of fabricating electronic instrument Information that is transferred through a bus BUS1 (conforming to IEEE 1394) is downloaded into a rewrite area storing device information (such as GUID or config ROM) and data transfer control program information (such as a SBP-2 firmware program), and rewrit... | 09/09/2008 |
| 7424564 | PCI—express slot for coupling plural devices to a host system A PCI-Express slot for coupling devices to a host system is provided. The slot includes a PCI-Express connector that can couple at least two devices using at least two independent PCI-Express lanes. Four, eight, twelve, sixteen, and/or thirty PCI-Express lanes are u... | 09/09/2008 |
| 7421532 | Switching with transparent and non-transparent ports There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports. ... | 09/02/2008 |
| 7421507 | Transmission of AV/C transactions over multiple transports method and apparatus Disclosed is a system and method for transmitting AV/C data over one or more transports. Further disclosed is a system and method for transmitting AV/C data over non-FCP communication media. The disclosed system and method includes an AV/C transaction delivery syste... | 09/02/2008 |
| 7418534 | System on a chip for networking A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more n... | 08/26/2008 |
| 7418521 | Controller for bridging a host computer and networked laundry machines A laundry system has a plurality of laundry machines networked together and a remotely located host computer for collecting operation data and audit data from the laundry machines and to program the laundry machines with operation parameters. A bridging controller i... | 08/26/2008 |
| 7418536 | Processor having systolic array pipeline for processing data packets A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of progr... | 08/26/2008 |
| 7415555 | Bus bridge device A bus bridge device, which connects a first device executing a first process and a second device executing a second process in response to a request from the first device, includes a notifying unit that notifies, when a result of the second process is received from ... | 08/19/2008 |
| 7412554 | Bus interface controller for cost-effective high performance graphics system with two or more graphics processing units A bus interface controller manages a set of serial data lanes. The bus interface controller supports operating a subset of the serial data lanes as a private bus. ... | 08/12/2008 |
| 7412588 | Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted pac... | 08/12/2008 |
| 7412553 | Enhanced protocol conversion system capable of providing offloaded protocol instruction processing Systems are provided for the offloading of protocol control and conversion information within microprocessor-based systems. A converter controller comprises a first interface and protocol, as well as a second interface and protocol. An intermediate protocol and inte... | 08/12/2008 |
| 7409486 | Storage system, and storage control method A protocol chip and a bridge are connected to a first bus, while the bridge and a micro processor (MP) are connected to a second bus. The MP generates parameter information and writes it into a local memory (LM), and issues a write command which includes access dest... | 08/05/2008 |
| 7406544 | Semiconductor integrated circuit A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The contro... | 07/29/2008 |
| 7406553 | System and apparatus for early fixed latency subtractive decoding Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus... | 07/29/2008 |
| 7404020 | Integrated fibre channel fabric controller A fibre channel switch element with an integrated fabric controller on a single chip is provided. The fabric controller including a processor module that can control various switch element functions; a serlizer/de-serializer for converting parallel data to serial da... | 07/22/2008 |
| 7398345 | Inter-integrated circuit bus router for providing increased security An inter-integrated circuit port for providing increased security. An electrical connector for communicative coupling to an inter-integrated circuit bus is provided. A controller coupled to the electrical connector operates to control data communication through the ... | 07/08/2008 |
| 7398346 | Bus system for use with information processing apparatus A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection control... | 07/08/2008 |
| 7395365 | Data transfer control system, electronic instrument, program, and data transfer control method A data transfer control system includes: a port control section which controls ports P1 and P2 respectively connected with an electronic instrument PC1 and an electronic instrument PC2; and a bus reset issue section which issues a bus res... | 07/01/2008 |
| 7380018 | Peripheral bus transaction routing using primary and node ID routing information A processing device includes one or more resources, a plurality of peripheral bus interfaces that support resource sharing with a plurality of other processing devices, a primary routing resources and a node ID register. The primary routing resources are programmabl... | 05/27/2008 |
| 7376777 | Performing an N-bit write access to an M×N-bit-only peripheral A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a wr... | 05/20/2008 |
| 7376778 | Audio device The present invention provides a digital bus circuit comprising: a bus conductor having two sections each connected to a pass circuit, each bus section being connected to two bus interfaces for respective circuits; at least three of the bus interfaces comprising a t... | 05/20/2008 |
| 7373487 | Controller with fail-safe function A master CPU and a slave CPU for processing data supplied from a detector unit, and a timer cleared by a clear signal supplied every predetermined time period from the master CPU when the operation of the master CPU is normal and adapted for supplying a reset signal... | 05/13/2008 |
| 7373450 | Multi-layer bus system having a bus control circuit A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports and slave connection ports, and connects one of the master connection ports to one of the slave connectio... | 05/13/2008 |
| 7373449 | Apparatus and method for communicating in an integrated circuit An integrated circuit comprising a plurality of processing modules (M; I; S; T) and a network (N; RN) arranged for providing at least one connection between a first and at least one second module is provided. Said connections comprises a set of communication channel... | 05/13/2008 |
| 7373555 | Systems and methods controlling transaction draining for error recovery Disclosed are systems and methods for controlling transaction draining for error recovery comprising asserting a control signal to prevent system resources associated with a particular error from issuing new requests, dropping transactions tracked by an out-of-order... | 05/13/2008 |
| 7372863 | Systems for monitoring and controlling operating modes in an ethernet transceiver and methods of operating the same Disclosed are systems and methods for monitoring and controlling operating modes in a network transceiver. In one embodiment, a computer system is associable with an Ethernet network, and comprises a processing unit, a memory and a transceiver. The transceiver compr... | 05/13/2008 |
| 7373444 | Systems and methods for manipulating entries in a command buffer using tag information Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the entries can be removed if the corresponding transactions are canceled. In one embodiment, multiple master de... | 05/13/2008 |
| 7370132 | Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock pow... | 05/06/2008 |
