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| Number | Title | Issue Date |
| 7117405 | Extender card with intercepting EEPROM for testing and programming un-programmed memory modules on a PC motherboard An extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. The extender card has an intercepting EEPROM chip that receives device-select lines from th... | 10/03/2006 |
| 7117287 | History FIFO with bypass wherein an order through queue is maintained irrespective of retrieval of data An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data it... | 10/03/2006 |
| 7117419 | Reliable communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 10/03/2006 |
| 7114043 | Ambiguous virtual channels An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherei... | 09/26/2006 |
| 7111103 | Method and apparatus for system management applications using a local controller A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of ... | 09/19/2006 |
| 7111104 | Methods and circuits for stacking bus architecture A system for connecting multiple repeaters into a single collision domain comprising a first repeater, a second repeater and a stacking bus. The first repeater has a plurality of network ports. The second repeater also has a plurality of network ports. The stacking ... | 09/19/2006 |
| 7107388 | Method for read once memory Flash memory in a computing system having blocks that may be read only once per machine reset may be implemented by mapping the flash memory to an address space of the computing system, copying a selected block of at least one of instructions and data from a first r... | 09/12/2006 |
| 7107383 | Method and system for multi-channel transfer of data and control information A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a ... | 09/12/2006 |
| 7107415 | Posted write buffers and methods of posting write requests in memory modules A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are al... | 09/12/2006 |
| 7107361 | Coupled computers and a method of coupling computers The present invention provides coupled-type computers wherein a computer can be coupled with computers of the same structure easily, and can be coupled with other computers of the same structure in high density. Computer components such as CPUs or memories are built... | 09/12/2006 |
| 7107373 | Method of hot switching data transfer rate on bus The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data trans... | 09/12/2006 |
| 7106611 | Wavelength division multiplexed memory module, memory system and method A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the memory hub. The controller communicates with the memory hubs by coupling optical signals to and from the... | 09/12/2006 |
| 7103691 | Method, system and device for a processor to access devices of different speeds using a standard memory bus A method for accessing a device, such as a memory device and an interface device, by a processor is disclosed. The method involves the processor requesting access permission for the transfer of data. The bridge device grants access permission. The processor in respo... | 09/05/2006 |
| 7103704 | Exporting 12C controller interfaces for 12C slave devices using IPMI micro-controller A system and method is provided that allows an Intelligent Platform Management Interface (IPMI) controller (or another micro-controller that is not a dedicated I2C controller) to control various Inter Integrated Circuit (I2C) slave devices having I2C slave drivers w... | 09/05/2006 |
| 7103823 | Communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 09/05/2006 |
| 7103695 | System and method for scaling a bus based on a location of a device on the bus A system and method for scaling a bus based on a location of a device on the bus are disclosed. An information handling system includes a host bridge interfaced between a local bus and a peripheral bus operable to run at a plurality of bus speeds generated by the ho... | 09/05/2006 |
| 7103696 | Circuit and method for hiding peer devices in a computer bus Circuit and method for hiding peer devices from a computer host are provided. The devices and host share a common electrical bus, e.g., a PCI bus. The method allows to generate a signal indicative of the presence of a first peer device. The method further allows to ... | 09/05/2006 |
| 7103636 | Methods and apparatus for speculative probing of a remote cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or ... | 09/05/2006 |
| 7103697 | Flow-through register A selectively transparent interface circuit identified herein as a flow-through register (FTR) is disclosed. The FTR enables one or more devices on a primary bus to communicate with a device on a secondary bus without incurring the latency and performance degradatio... | 09/05/2006 |
| 7103013 | Bidirectional bridge circuit having high common mode rejection and high input sensitivity A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate diffe... | 09/05/2006 |
| 7103700 | Method of and apparatus for controlling bidirectional streams of isochronous data flowing between an application and a bus structure An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of ... | 09/05/2006 |
| 7099345 | Method and system for buffering a data packet for transmission to a network Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag use... | 08/29/2006 |
| 7099968 | System and method for generating bus requests in advance based on speculation states A system and method predict when to generate a bus request ahead-of-time based on bus-activity, bus-usage efficiency and bus-bandwidth usage. A bus-usage efficiency indicator may be generated by a requester, such as a memory controller, based on a number of unused b... | 08/29/2006 |
| 7099814 | I/O velocity projection for bridge attached channel An impact of configuration changes on controllers is projected, in a computing environment including one or more bridge attached channels. This projection quantifies the impact for each controller affected by the change, such that it is known by a quantifiable value... | 08/29/2006 |
| 7099966 | Point-to-point electrical loading for a multi-drop bus A switching technique allows multiple interconnect bus devices to be connected to a single bus segment, even if the interconnect bus protocol only allows a one of the interconnect devices to be connected at any time. Each of the interconnect devices is connected to ... | 08/29/2006 |
| 7099986 | High speed peripheral interconnect apparatus, method and system A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconne... | 08/29/2006 |
| 7099984 | Method and system for handling interrupts and other communications in the presence of multiple processing sets A computing system comprises two or more processing sets, for example for fault tolerant operation. The multiple processing sets have a connection to at least one device, typically many devices. The ownership of each device is allocated to one of the two or more pro... | 08/29/2006 |
| 7100068 | Panel device for adjusting computer's operating frequency and showing system information A panel device mounted on a computer case comprises an adjustment unit for adjusting CPU's operating frequency, a display module for showing system information, and a microprocessor which interconnects the adjustment unit and the display module with the computer sys... | 08/29/2006 |
| 7099983 | Multi-core communications module, data communications system incorporating a multi-core communications module, and data communications process A communications module for a data communications system having a plurality of data processors comprises a plurality of ports, each coupled to a respective one of the data processors. An address table associates addresses of a memory space to addresses of the data p... | 08/29/2006 |
| 7099973 | Method and system of bus master arbitration A system (100) having a plurality of bus masters (111–113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and se... | 08/29/2006 |
| 7096468 | Programmer/feeder system task linking program A task linking program is provided for using a computer for interacting with on-line and off-line programming systems to perform tasks related to programming microdevices. The program is secure in being capable of being setup only in an administrator mode where micr... | 08/22/2006 |
| 7096303 | Method and apparatus for configuring an integrated bus A configurable bus interface circuit includes an internal bus bridge and an internal circuit. The configurable bus interface circuit also includes an internal I/O circuit couplable to an external circuit, via the internal bus bridge. The configurable bus interface c... | 08/22/2006 |
| 7096308 | LPC transaction bridging across a PCIexpress docking connection A hybrid PCI_Express fabric system allows LPC bus commands and data to be sent across the PCI_Express fabric from a portable computer to its docking station. This permits the portable computer to be coupled to peripheral devices connected to the docking station with... | 08/22/2006 |
| 7096309 | Computing device capable of instant-on and non-instant on modes of operation A single, dual form computing device is provided that incorporates the functionality of a laptop computer with that of a handheld or palm-size computing device, and allows each functionality to be selectively employed. The dual form computing device operates in one ... | 08/22/2006 |
| 7096304 | Apparatus and method for managing voltage buses The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge c... | 08/22/2006 |
| 7096290 | On-chip high speed data interface An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit ca... | 08/22/2006 |
| 7095415 | Graphics display architecture and control chip set thereof The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the... | 08/22/2006 |
| 7096305 | Peripheral bus switch having virtual peripheral bus and configurable host bridge A peripheral bus switch includes a virtual peripheral bus, a plurality of bridges, and a configurable host bridge. A first bridge operably couples on a first side to the virtual peripheral bus and supports connection on a second side to a peripheral bus fabric. A se... | 08/22/2006 |
| 7096307 | Shared write buffer in a peripheral interface and method of operating A data processing system has a single configurable write buffer within a peripheral interface unit that is shared among multiple peripherals. Configuration registers are dynamically programmed to control criteria for determining whether control of a system bus will ... | 08/22/2006 |
| 7093052 | Bus sampling on one edge of a clock signal and driving on another edge An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling) of the clock signal and to sample signals responsive to the second edge. The sampled signals may be eval... | 08/15/2006 |
