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| Number | Title | Issue Date |
| 6925349 | Device and method for synchronizing a plurality of electric drive units in a paper processing machine The present invention relates to a device and a method for synchronizing processes which are executed on a plurality of units (2a, 2b, 2c), in particular, in paper-processing machines, the units (2a, 2 | 08/02/2005 |
| 6922752 | Storage system using fast storage devices for storing redundant data A computer storage system includes a controller and a storage device array. The storage device array may include a first sub-array and a fast storage device sub-array. The first sub-array includes one or more first storage devices storing data. The fast storage devi... | 07/26/2005 |
| 6920519 | System and method for supporting access to multiple I/O hub nodes in a host bridge Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling ro... | 07/19/2005 |
| 6915357 | Control apparatus and control method Complex control procedures employ direct memory access by a first DMA processing unit 54 to send control data to a first controller by means of DMA channels 54-1 to 54-n, and by a second DMA processing unit 56 to sen... | 07/05/2005 |
| 6914892 | Arrangement for testing network switch expansion port data by converting to media independent interface format A method for testing a network switch chip having an expansion port configured for transferring data according to a prescribed expansion port protocol. The method includes outputting the expansion port frame data from the expansion port according to the prescribed e... | 07/05/2005 |
| 6915503 | Methods of utilizing noise cores in PLD designs to facilitate future design modifications Methods of using “noise cores” in a PLD design. “Noise cores” are pre-developed blocks of logic included in a PLD design for the purpose of creating noise in other circuits also implemented in the PLD. By gradually increasing the level of noise created by th... | 07/05/2005 |
| 6915475 | Data integrity management for data storage systems A system and method for maintaining the integrity of data in a storage system. The method includes receiving a plurality of blocks of data having a predetermined multiple-block error detecting code; reading each block of the blocks of data; generating, for each bloc... | 07/05/2005 |
| 6912598 | Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selectiv... | 06/28/2005 |
| 6910083 | Method for detecting channels of a host to which hard disk controllers belong A method for detecting channels of a host to which hard disk controllers belong is used to detect the connection relations between several channels of a host and several removable hard disk cases in the hard disk device. Each of the removable hard disk cases has a c... | 06/21/2005 |
| 6907477 | Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality o... | 06/14/2005 |
| 6901456 | Method and system for SCSI host bus interconnection A method and system for selectively interconnecting two SCSI host buses where each SCSI host bus includes a host device and multiple addressable SCSI target devices, each SCSI target device having a multibit SCSI ID associated therewith. A SCSI cross-link repeater i... | 05/31/2005 |
| 6898643 | Device and method for controlling access to computer peripherals The invention concerns the sharing and the controlling of access to at least one peripheral for a computer system which includes a central processing unit and at the least one peripheral which has a physical interface to the central processing unit. Specifically, a ... | 05/24/2005 |
| 6895453 | System and method for improved handling of fiber channel remote devices In traditional Fiber Channel systems, remote devices connected to the Fiber Channel network using a bridge or included in a storage enclosure are not tracked. If a remote device, such as a SCSI disk device, is removed or swapped, data errors such as data corruption ... | 05/17/2005 |
| 6892268 | Heterogeneous computer system, heterogeneous input/output system and data back-up method for the systems A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least... | 05/10/2005 |
| 6889268 | Multi-chip system having a continuous burst read mode of operation Embodiments of the invention provide a multi-chip system that includes a first and a second semiconductor memory device. The memory devices are mounted in a single package. The multi-chip system has a continuous burst read mode of operation, in which a read operatio... | 05/03/2005 |
| 6886171 | Caching for I/O virtual address translation and validation using device drivers A method and apparatus for input/output virtual address translation and validation assigns a range of memory to a device driver for its exclusive use. The device driver invokes system functionality for receiving a logical address and outputting a physical address ha... | 04/26/2005 |
| 6880022 | Transparent memory address remapping A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is able to address a second space of the hardware memory using second identi... | 04/12/2005 |
| 6871255 | Heterogeneous computer system, heterogeneous input/output system and data back-up method for the systems A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least... | 03/22/2005 |
| 6868492 | Methods and apparatus for booting a host adapter device devoid of nonvolatile program memory Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operati... | 03/15/2005 |
| 6865618 | System and method of assigning device numbers to I/O nodes of a computer system A system and method of assigning device numbers to a plurality of I/O nodes of a computer system. Each of the plurality of input/output nodes is initialized to a common default device number. The method includes assigning a unique device number such as a Unit ID, fo... | 03/08/2005 |
| 6865617 | System maps SCSI device with virtual logical unit number and multicast address for efficient data replication over TCP/IP network The present invention combines IP multicasting mechanisms with SCSI protocols to achieve a more efficient data replication or data mirroring scheme. The combination of the IP multicast mechanism with the mapping of virtual unit logical number to real logical unit nu... | 03/08/2005 |
| 6850992 | Address assignment method for at least one bus device that has recently been connected to a bus system A bus device that has recently been connected to a bus system is first addressable at a pre-set address. A bus master transmits a new address and an identification to the bus device. The bus device compares the transmitted identification with an identification that ... | 02/01/2005 |
| 6848007 | System for mapping addresses of SCSI devices between plurality of SANs that can dynamically map SCSI device addresses across a SAN extender The present invention provides a method and system for mapping addressing of SCSI devices between two SANs connected by a SAN extender over a packet-based network with use of a Fibre channel protocol over large distances. The present invention seamlessly interconnec... | 01/25/2005 |
| 6845439 | Method and system for accessing an expanded SCB array A method for accessing hardware I/O control blocks, which are stored in an hardware I/O control block array, by a parallel SCSI host adapter addresses one page in a plurality of pages of the hardware I/O control block array for the parallel SCSI host adapter using a... | 01/18/2005 |
| 6839764 | Domain encapsulation A system for processing Internet requests that permits multiple binds to the same socket number at the same time on the same computer. A separate domain processing shell may be provided for each domain being hosted on a particular platform, and each domain may be ma... | 01/04/2005 |
| 6834321 | Communication method of a serially connected electronic apparatus Controlling each of a plurality of serially connected electronic apparatuses without increasing the number of signal lines is provided. In an electronic apparatus, from among a plurality of electronic apparatuses serially connected to a computer, a control command s... | 12/21/2004 |
| 6832267 | Transmission method, transmission system, input unit, output unit and transmission control unit To enable setting for transmission through network such as IEEE1394 system with input plugs freely, when transmitting data obtained in an output device connected to a predetermined network to the network from a predetermined output plug of the output device and rece... | 12/14/2004 |
| 6829762 | Method, apparatus and system for allocating and accessing memory-mapped facilities within a data processing system Within a data processing system, a pool of facilities are allocated to an operating system, where each facility within the pool of facilities has an associated real address. The operating system allocates from the pool at least one bypass facility to a first process... | 12/07/2004 |
| 6826354 | Buffer control method and buffer control device A buffer control device for controlling a buffer memory includes a comparing unit which compares input data with one or more data patterns, a control unit which stores a code which indicates a data pattern among data patterns into said buffer memory if the input dat... | 11/30/2004 |
| 6823431 | Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency The multi-processor system according to the present invention includes at least two processors, a system bus providing communication between the responses to commands on the system bus. One of the processors generates a snoop response to a command, associated with t... | 11/23/2004 |
| 6820139 | Method and architecture to associate enclosure service data with physical devices on a fibre channel loop with soft addresses An apparatus comprising one or more drive portions and a controller. The one or more drive portions may each comprise one or more drives. The controller may be configured to map correctly correlating addresses to the one or more drives. ... | 11/16/2004 |
| 6819323 | Structure and method for gaining fast access to pixel data to store graphic image data in memory A memory chip having fast access to pixel data of graphics image to be stored therein is described. The memory chip consists of data inputs and outputs (I/Os) divided into a plurality of blocks; memory arrays for storing data received from or sent to the I/Os, which... | 11/16/2004 |
| 6816379 | External storage device unit, and information processor having the same The external storage device unit of the present invention comprises a cover for blocking an opening of a main body casing for storing an external storage device. Connectors for a storage device side connected to external connection connectors of the external storage... | 11/09/2004 |
| 6813646 | Controlling electronics across an RF barrier using a serial interface bus A method for controlling electronics across an RF barrier is disclosed. The method comprises a serial data control method that requires a limited number of signals passing through an RF barrier and does not require a free running clock. This method uses a processor ... | 11/02/2004 |
| 6812596 | Safety switching device module arrangement The invention relates to a module arrangement of safety switching devices. The arrangement comprises a plurality of input modules each for processing input signals from a safety transmitter and each for generating output signals. It further comprises at least two ou... | 11/02/2004 |
| 6807584 | Apparatus and method for exchanging status information between boards An apparatus and method for exchanging information between printed circuit board assemblies of the present invention are disclosed. According to the invention, the number of address pins are assigned according to the amount of information to be exchanged between the... | 10/19/2004 |
| 6807600 | Method, system, and program for memory based data transfer Provided are a method, system, and program for a local bus system. A memory address space in configured to control an I/O device. The memory address space is associated with a port coupled to the local bus system. ... | 10/19/2004 |
| 6799231 | Virtual I/O device coupled to memory controller The invention relates to a virtual I/O device coupled to a memory controller in a microprocessor of computer, the virtual I/O device and a memory unit being in communication with the memory controller via a common interface so that any of a plurality of peripherals ... | 09/28/2004 |
| 6792478 | System and method to configure input/output (IO) devices to use selected pairs of port addresses The present invention relates to a system and method to configure input/output (SIO) devices to use selected pairs of port addresses. The method includes writing a first unique value to a selected port address. The method further includes writing a second unique val... | 09/14/2004 |
| 6792520 | System and method for using a using vendor-long descriptor in ACPI for the chipset registers A system and method for using memory mapped I/O (MMIO) to manage system devices is provided. A parent device in the ACPI namespace uses (MMIO) to identify the memory addresses of its children devices. An existing, but unused, construct of ACPI is used to pass the MM... | 09/14/2004 |
