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An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
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| Number | Title | Issue Date |
| 4723205 | Micro computer system A microcomputer system has two central processing units, an original and one added to expand the system, each having an associated memory and being interconnected through an appropriate signal bus arrangement, however, only the first or original central p... | 02/02/1988 |
| 4707802 | Semiconductor integrated circuit device selected by an address signal A semiconductor IC device such as a peripheral interface LSI device used in a data processing system comprises an address memory for storing the chip address of the device itself and a comparator for comparing an address signal input thereto from an exter... | 11/17/1987 |
| 4654791 | Input/output paging mechanism in a data processor In a data processor performing an input and output paging function, a main memory (MMU) and an input and output processor (IOP) connected to the MMU through a bus are provided. The MMU stores a list-service page table for mapping a logical space in which ... | 03/31/1987 |
| 4593352 | Method and device for exchanging information between terminals and a central control unit Information exchange method in a communications controller comprising a central control unit (CCU) associated with a storage that provides a number of parameter/status and data areas equal to the maximum number of interfaces to be managed by the controlle... | 06/03/1986 |
| 4591973 | Input/output system and method for digital computers An input/output (I/O) system and method for coupling a host computer to a plurality of peripheral devices in which data destined for peripheral devices is transferred to an output data buffer whose locations are paired with output channel addresses stored... | 05/27/1986 |
| 4547849 | Interface between a microprocessor and a coprocessor A nonclock-synchronous interface between a microprocessor and a coprocessor. A request line (404) from the coprocessor and an acknowledgment line (402) from the microprocessor provide for operand transfer from the coprocessor to the microprocessor. A busy... | 10/15/1985 |
| 4533996 | Peripheral systems accommodation of guest operating systems A peripheral system attached to a host having plural virtual machines accommodates the virtual machines via "guest" attribute signals signifying that a given chain of peripheral or I/O commands are virtual machine sourced (GO bit). The attribute signals m... | 08/06/1985 |
| 4450521 | Digital processor or microcomputer using peripheral control circuitry to provide multiple memory configurations and offset addressing capability An electronic digital processor system including an internal memory for the storage of data and commands, an arithmetic and logic unit, a register set, data paths and control/timing circuitry together with peripheral control circuitry which provides a num... | 05/22/1984 |
| 4407016 | Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor A microprocessor receives addresses and data from a peripheral subsystem for use in subsequently accessing portions of the main memory of a data processing system in a controlled and protected manner. Each of the addresses is used to interrogate an associ... | 09/27/1983 |
| 4387441 | Data processing system wherein at least one subsystem has a local memory and a mailbox memory within the local memory for storing header information A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus include... | 06/07/1983 |
| 4383297 | Data processing system including internal register addressing arrangements In a multi-processor system of the type in which each processor is provided with its own unique bus which has an addressing system organized in such a manner that all store locations and peripheral equipments are addressed as part of a comprehensive singl... | 05/10/1983 |
| 4320456 | Control apparatus for virtual address translation unit Control apparatus is responsive to CPU I/O commands for initiating chained I/O data transfers to cause virtual address translation (VAT) apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translat... | 03/16/1982 |
| 4315310 | Input/output data processing system An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address spa... | 02/09/1982 |
| 4314334 | Serial data communication system having simplex/duplex interface A data communication system having a master unit, an interface, and one or more remote units. The master unit includes a programmable controller having a data processor, memory storage for storing programs and command and data bytes, and address and data ... | 02/02/1982 |
| 4245303 | Memory for data processing system with command and data buffering A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, a... | 01/13/1981 |
| 4231088 | Allocating and resolving next virtual pages for input/output In a paged, virtual memory computer system an apparatus is provided for enabling I/O device adapters to request the CPU to allocate or resolve virtual pages into main storage pages as required for I/O data transfers. The I/O adapter provides the channel v... | 10/28/1980 |
| 4228504 | Virtual addressing for I/O adapters In a paged, virtual memory computer system, apparatus is provided for enabling I/O adapters to use virtual addresses. After each I/O data transfer, the main memory address involved in the transfer is incremented. This address is maintained in an I/O regis... | 10/14/1980 |
| 4173783 | Method of accessing paged memory by an input-output unit In a data processing system employing paging and segmentation for storing information in memory, the input-output unit is provided with addressing capability for addressing and accessing memory without the intervention of the central processing unit to co... | 11/06/1979 |
| 4156932 | Programmable communications controller A programmable communications controller having a microcomputer system for buffering and controlling data communications between a communication processor and a plurality of input/output (I/O) ports of the microcomputer system to which ports/terminals can... | 05/29/1979 |
| 4126897 | Request forwarding system Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to wh... | 11/21/1978 |
| 4096565 | Integrated circuit data handling apparatus for a data processing system, having a plurality of modes of operation A data handling apparatus of solid state construction for a data processing system. The apparatus has a storage and input/output gates for peripheral units. The storage includes input and output counters for generating storage addresses which, respectivel... | 06/20/1978 |
| 3949380 | Peripheral device reassignment control technique A plurality of peripheral devices having physical addresses are accessed by a host processor by use of logical addresses which are utilized by the various programs in a multiprocessing environment. Input/output tables are arranged to include pointers for ... | 04/06/1976 |
