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| Number | Title | Issue Date |
| 7945714 | Apparatus and method of tracing descriptors in host controller Apparatus and method of tracing descriptor in a host controller are provided. The host controller for controlling a device includes a first bus interface coupled to a system bus, a processor which determines whether data received from a system memory through the fir... | 05/17/2011 |
| 7844754 | Data transfer apparatus and data transfer method A data transfer apparatus includes a processor, a main memory, and a DMAC connected to the main memory via a plurality of buses. The DMAC transfers data to the main memory by bypassing the processor, writes flag data “1” indicating completion of the data transfe... | 11/30/2010 |
| 7805547 | Process and device for the transmission of data between a processor and a mass memory unit A process for the transmission of data between a processor and a mass memory unit, initialization and/or control commands are transmitted via a PCMCIA interface to the mass memory unit, while user data, however, are transmitted via a memory interface. Accordingly, a... | 09/28/2010 |
| 7716391 | Data transfer apparatus, data transfer method, and program A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information o... | 05/11/2010 |
| 7451250 | Methods and apparatus for providing automatic high speed data connection in portable device In a portable FireWire compatible device, a direct memory access (DMA) bus switch coupled by way of a DMA bus to a central processing unit (CPU), a local hard drive (HDD), and a FireWire port, provides a direct connection between the FireWire port and the HDD bypass... | 11/11/2008 |
| 7444441 | Device including means for transferring information indicating whether or not the device supports DMA A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct memory access. ... | 10/28/2008 |
| 7404015 | Methods and apparatus for processing packets including accessing one or more resources shared among processing engines Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets... | 07/22/2008 |
| 7380115 | Transferring data using direct memory access A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the prima... | 05/27/2008 |
| 7370131 | High-speed data readable information processing device A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal.... | 05/06/2008 |
| 7350015 | Data transmission device A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it has connections for connecting at least two data buses and can output d... | 03/25/2008 |
| 7328300 | Method and system for keeping two independent busses coherent Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and th... | 02/05/2008 |
| 7313641 | Inter-processor communication system for communication between processors A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a pr... | 12/25/2007 |
| 7301580 | Method of realizing combination of multi-sets of multiple digital images and bus interface technique A method of digital image combination for multiple channels with multiple sets and a bus interface which includes an image-processing unit for m-channel sub-images, an image-processing unit for n-set combining images, n-set video data buses, address and control buse... | 11/27/2007 |
| 7301541 | Programmable processor and method with wide operations A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present ... | 11/27/2007 |
| 7302699 | Logged-in device and log-in device A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous lo... | 11/27/2007 |
| 7286067 | Appliance with communication protocol emulation An appliance includes a physical interface for communication according to a broad protocol and two functional components. The first functional component communicates via the physical interface. The second functional component includes a functional module adapted to ... | 10/23/2007 |
| 7259876 | Image processing apparatus, and, control method and control device therefor A first storage stores input image data. A second storage stores image data read from the first storage. A control part determines, with respect to a timing at which data transfer of image data into the first storage, a data transfer of the said image data from the ... | 08/21/2007 |
| 7260015 | Memory device and method having multiple internal data buses and memory bank interleaving A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of int... | 08/21/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7228404 | Managing instruction side-effects A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the represe... | 06/05/2007 |
| 7228367 | Direct memory access controller for carrying out data transfer by determining whether or not burst access can be utilized in an external bus and access control method thereof An address region of an internal bus wherein a burst access can be utilized in an external bus is set in an address table. A DMA control unit determines whether or not a burst access can be utilized in the external bus by comparing an address in an access to the int... | 06/05/2007 |
| 7219169 | Composite DMA disk controller for efficient hardware-assisted data transfer operations In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations i... | 05/15/2007 |
| 7209405 | Memory device and method having multiple internal data buses and memory bank interleaving A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of int... | 04/24/2007 |
| 7209995 | Efficient connection between modules of removable electronic circuit cards A removable electronic circuit card has multiple modules connected to the card's bus in parallel so that each module can exchange commands and data independently with the host. According to a first aspect of the present invention, this achieved by a controller-to-co... | 04/24/2007 |
| 7206873 | Throughput optimization by activation of selected parallel channels in a multichannel tape drive The present invention describes a method and system for adjusting the rate of data transfer between a high-speed multi-channel tape drive and a slower-capability network interface. The present invention allows for selectively enabling/disabling active channels to ad... | 04/17/2007 |
| 7200693 | Memory system and method having unidirectional data buses A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each... | 04/03/2007 |
| 7177960 | Mobile terminal To display a horizontally oblong movie on a vertically oblong display portion, the movie may be displayed with being rotated 90 degrees by a CPU while the display portion is held in an orientation where the display portion is wider than tall. Since this arrangement ... | 02/13/2007 |
| 7165125 | Buffer sharing in host controller A storage device host controller such as an SATA (Serial ATA) host controller and a corresponding method are provided for performing host-to-device and device-to-host communications in a PIO (Programmed I/O) data transfer mode and a DMA (Direct Memory Access) data t... | 01/16/2007 |
| 7155572 | Method and apparatus for injecting write data into a cache A data processing system (100, 600) has a memory hierarchy including a cache (124, 624) and a lower-level memory system (170, 650). A data element having a special write with inject attribute is received from a data producer (160, 640), s... | 12/26/2006 |
| 7149823 | System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a prefe... | 12/12/2006 |
| 7137110 | Profiling ranges of execution of a computer program Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a p... | 11/14/2006 |
| 7136943 | Method and apparatus for managing context switches using a context switch history table A method, apparatus and computer instructions for storing data relating to the switch in a context switch history containing a number of prior context switches occurring prior to a current context. The storing of data occurs in response to a change in context for a ... | 11/14/2006 |
| 7130933 | Method, system, and program for handling input/output commands Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the ... | 10/31/2006 |
| 7127534 | Read/write command buffer pool resource management using read-path prediction of future resources A method for managing read and write data congestion in a system for executing write and read data commands and having a buffer pool of blocks for temporarily storing read and write data is disclosed. Management of the buffer pool and the initiation of read and writ... | 10/24/2006 |
| 7114014 | Method and system for data movement in data storage systems employing parcel-based data mapping Embodiments of the present invention provide methods and systems for data movement in data storage systems. For one embodiment, a physical data storage parcel containing a first type of data requiring a first type of processing and a second type of data requiring a ... | 09/26/2006 |
| 7111290 | Profiling program execution to identify frequently-executed portions and to assist binary translation A method and a computer with circuitry configured for performance of the method are disclosed. During a profiled interval of an execution of a program on a computer, profile information is recorded describing the execution, without the program having been compiled f... | 09/19/2006 |
| 7106326 | System and method for computing filtered shadow estimates using reduced bandwidth A graphical processing system comprising a computational unit and a shadow processing unit coupled to the computational unit through a communication bus. The computational unit is configured to transfer coordinates C1 of a point P with respect to a first ... | 09/12/2006 |
| 7099345 | Method and system for buffering a data packet for transmission to a network Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag use... | 08/29/2006 |
| 7089344 | Integrated processor platform supporting wireless handheld multi-media devices A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coup... | 08/08/2006 |
| 7075565 | Optical inspection system An automated optical inspection system includes a plurality of asynchronously triggerable cameras for providing image data of an object, such as a printed circuit board. The circuit board is divided into fields of view that are to be imaged in one or more cameras in... | 07/11/2006 |
