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| Number | Title | Issue Date |
| 8103816 | Technique for communicating interrupts in a computer system A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or ope... | 01/24/2012 |
| 8051234 | Multiprocessor system The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt... | 11/01/2011 |
| 7953916 | Dynamic, local retriggered interrupt routing discovery method In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC/AT compatible. In a mobile Internet device (MID) General Pur... | 05/31/2011 |
| 7783809 | Virtualization of pin functionality in a point-to-point interface Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor ... | 08/24/2010 |
| 7783810 | Apparatus and method of processing information An information processing apparatus is provided. Plural processors respectively execute separate operating systems to process data that has been received from a network. The apparatus includes receiving device that receives the data in predetermined units from the n... | 08/24/2010 |
| 7783811 | Efficient interrupt message definition An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are ... | 08/24/2010 |
| 7769938 | Processor selection for an interrupt identifying a processor cluster In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the inte... | 08/03/2010 |
| 7725637 | Methods and apparatus for generating system management interrupts A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interpr... | 05/25/2010 |
| 7721035 | Multiprocessor system, processor and interrupt control method A first processor in a multiprocessor system for processing interrupts by a plurality of processors accepts an interrupt and executes first interrupt processing in accordance with the accepted interrupt. In the first interrupt processing, second interrupt processing... | 05/18/2010 |
| 7707344 | Interrupt mitigation on multiple network adapters A method, information processing system, and computer readable medium, mitigate processor assignments. A first processor in a plurality of processors is assigned to a first communication port in a plurality of communication ports. An interrupt associated with the fi... | 04/27/2010 |
| 7689750 | System and method to dynamically order system management interrupt handler dispatches Handling interrupts within an information handling system including entering into an interrupt management mode in response to receiving an interrupt, identifying at least one source of the received interrupt in accordance with an ordered list of a plurality of possi... | 03/30/2010 |
| 7657684 | USB interrupt endpoint sharing A single USB interrupt endpoint is usable by two different active logical devices in a USB device. If a first logical device is to interrupt a USB host, then the first logical device writes a notification into the endpoint. The notification carries a number that ide... | 02/02/2010 |
| 7627706 | Creation of logical APIC ID with cluster ID and intra-cluster ID In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Ea... | 12/01/2009 |
| 7613861 | System and method of obtaining error data within an information handling system A system and method of obtaining error data within an information handling system is disclosed. According to one aspect, an interrupt handling system can include a first system management interrupt handler operable to initiate access to a first interrupt event messa... | 11/03/2009 |
| 7543096 | Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory A fault-tolerant mass storage system includes two RAID controllers that communicate via a PCI-Express link. Each controller has a bus bridge coupled to the link, a cache memory that caches user data for storage on disk drives controlled by the controllers, and a CPU... | 06/02/2009 |
| 7526592 | Interrupt control system and storage control system using the same An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge se... | 04/28/2009 |
| 7415557 | Methods and system for providing low latency and scalable interrupt collection A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an interrupt controller, outputting an interrupt command from the interrupt c... | 08/19/2008 |
| 7409483 | Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to proper... | 08/05/2008 |
| 7398343 | Interrupt processing system An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to di... | 07/08/2008 |
| 7366814 | Heterogeneous multiprocessor system and OS configuration method thereof Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt... | 04/29/2008 |
| 7363410 | Flexible interrupt handling methods for optical network apparatuses with multiple multi-protocol optical networking modules An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers to handle interrupts triggered by the function blocks of multi-protocol... | 04/22/2008 |
| 7363407 | Concurrent arbitration of multidimensional requests for interrupt resources The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an in... | 04/22/2008 |
| 7363409 | Interrupt control system and method for reducing interrupt latency An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one event signal. The control logic provides at least one computer executable ... | 04/22/2008 |
| 7353312 | Method and apparatus for detecting conditions for blocking a CPU's receipt of signals returned from a peripheral device A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU, wherein the return signal is a signal transmitted by a system chip in r... | 04/01/2008 |
| 7343474 | Minimal address state in a fine grain multithreaded processor In one embodiment, a processor comprises a plurality of pipeline stages and a first circuit operable at a first pipeline stage of the plurality of pipeline stages. The first circuit is configured to maintain a plurality of program counters (PCs), each of which corre... | 03/11/2008 |
| 7343527 | Recovery from iSCSI corruption with RDMA ATP mechanism A method and system for detecting and managing an error detected in an iSCSI (Internet Small Computer System Interface) PDU (Protocol Data Unit) by using a RDMA (Remote Direct Memory Access) dedicated receive error queue for error recovery. ... | 03/11/2008 |
| 7340547 | Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an ... | 03/04/2008 |
| 7340740 | Cooperatively multitasking in an interrupt free computing environment Multitasking in a hardware interrupt free environment. Event indicators are employed to multitask between processes of the environment. Processes to be multitasked register with one another, and then during processing, one of the processes toggles an event indicator... | 03/04/2008 |
| 7328294 | Methods and apparatus for distributing interrupts The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and peripheral interfaces. Interrupts and their associated characteristics a... | 02/05/2008 |
| 7328295 | Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated... | 02/05/2008 |
| 7328296 | Interrupt processing system An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to di... | 02/05/2008 |
| 7325084 | Messages signaling interrupt (MSI) processing system An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to di... | 01/29/2008 |
| 7320044 | System, method, and computer program product for interrupt scheduling in processing communication Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving computer program, coupling at least one registered signal identifier and a ... | 01/15/2008 |
| 7315911 | Method for efficient inter-processor communication in an active-active RAID system using PCI-express links A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it inter... | 01/01/2008 |
| 7302512 | Interrupt steering in computing devices to effectuate peer-to-peer communications between device controllers and coprocessors A computer device, an input/output (“I/O”) communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications between a device controller and a coprocessor. Advantageously, the vario... | 11/27/2007 |
| 7293123 | Asymmetric data path media access controller A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ... | 11/06/2007 |
| 7266628 | System and method of retiring events upon device replacement An information handling system is disclosed that retires events upon device replacement. The system has several devices of one or more types and each device includes nonvolatile memory. A unique identifier, for devices of that type, is stored in the nonvolatile memo... | 09/04/2007 |
| 7263568 | Interrupt system using event data structures Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in resp... | 08/28/2007 |
| 7259881 | Method of monitoring multiple controller families A method is disclosed including the steps of submitting a print job to a network printer and identifying a specific printer controller governing the print job. The method further includes loading a set of identifiers respective to a specific printer controller and s... | 08/21/2007 |
| 7257658 | Message based interrupt table An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status informatio... | 08/14/2007 |
