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| Number | Title | Issue Date |
| 8151028 | Information processing apparatus and control method thereof An information processing apparatus connected with an IO device, having a processing unit, a channel device transferring data between the information processing apparatus and the IO device having a activation controller activating the channel device, a storage devic... | 04/03/2012 |
| 8135894 | Methods and systems for reducing interrupt latency by using a dedicated bit A system and a method for reducing interrupt latency is described. The system includes a first interrupt source configured to generate a first interrupt, a second interrupt source configured to generate a second interrupt, and a processor. The processor includes a s... | 03/13/2012 |
| 8127064 | Method of managing the software architecture of a radio communication circuit, corresponding application, computer program product and circuit A method of managing the software architecture of a radio communication circuit is provided. The software architecture includes a radio communication software stack and at least one client application. The radio communication software stack includes a radio communic... | 02/28/2012 |
| 8103815 | Lazy handling of end of interrupt messages in a virtualized environment Techniques enable reducing a number of intercepts performed by a hypervisor by reducing a number of End Of Interrupt (EOI) messages sent from a virtual central processing unit (CPU) to a virtual advanced programmable interrupt controller (APIC). The EOI path of the ... | 01/24/2012 |
| 8032680 | Lazy handling of end of interrupt messages in a virtualized environment Techniques enable reducing a number of intercepts performed by a hypervisor by reducing a number of End Of Interrupt (EOI) messages sent from a virtual central processing unit (CPU) to a virtual advanced programmable interrupt controller (APIC). The EOI path of the ... | 10/04/2011 |
| 7945720 | Terminal apparatus and method for controlling processing of an interrupt event In a terminal apparatus, the central control section 1-10 judges whether or not a function accompanied with an audio output is in operation when a change in a folding opening/closing state of the terminal apparatus is detected by the folding open/close... | 05/17/2011 |
| 7849247 | Interrupt controller for accelerated interrupt handling in a data processing system and method thereof A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same inter... | 12/07/2010 |
| 7805557 | Interrupt controller and method for handling interrupts An interrupt controller and method are provided for handling interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises pend logic for receiving interrupt requests generated by the plurality of interrupt sources, and for eac... | 09/28/2010 |
| 7793025 | Hardware managed context sensitive interrupt priority level control A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified... | 09/07/2010 |
| 7769937 | Data processing system with interrupt controller and interrupt controlling method A data processing system includes a first interrupt controller with an interrupt source interface, an interrupt controller interface, a prioritizer, and an interrupt controller output. The data processing system further includes a processing unit providing an interr... | 08/03/2010 |
| 7689749 | Interrupt control function adapted to control the execution of interrupt requests of differing criticality An interrupt controller (1) is adapted to control the execution of interrupt requests (11, 12) of differing criticality by a processor (7) which is required to execute tasks (3, 17) of differing criticality under the control of a computer... | 03/30/2010 |
| 7685347 | Interrupt controller for invoking service routines with associated priorities An interrupt controller efficiently manages execution of tasks by a multiprocessor computing system. The interrupt controller has inputs for receiving service requests for invoking service routines. The service routines have higher priorities than the tasks executed... | 03/23/2010 |
| 7617346 | Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses th... | 11/10/2009 |
| 7552261 | Configurable prioritization of core generated interrupts A method and apparatus for generating an interrupt vector associated with either core (internal) generated or off-core (external) generated interrupts is provided. The apparatus includes a number of programmable interrupt priority level fields for storing priority l... | 06/23/2009 |
| 7484024 | Apparatus and method for interrupt source signal allocation An apparatus and method for interrupt source signal allocation is provided. An interrupt controller may include an interrupt source allocation unit, an interrupt pending register, a control register, a priority register, and/or an interrupt request signal generator.... | 01/27/2009 |
| 7472214 | Real-time embedded simple monitor method and computer product A processor context stored in a stack area at a time of an interrupt occurrence is saved in a context saving area of an ICB corresponding to an ISR that is interrupted. The ISR corresponding to the interrupt is set to an execution-waiting state. An ICB having a high... | 12/30/2008 |
| 7444450 | Method and system for detecting excessive interrupt processing for a processor A method and system is provided for detecting excessive interrupt processing for a processor. The method includes the operation of defining an interrupt processing period during which measuring of interrupts for a processor takes place. The amounts of time being spe... | 10/28/2008 |
| 7433985 | Conditional and vectored system management interrupts An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is bro... | 10/07/2008 |
| 7426728 | Reducing latency, when accessing task priority levels One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt ... | 09/16/2008 |
| 7415557 | Methods and system for providing low latency and scalable interrupt collection A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an interrupt controller, outputting an interrupt command from the interrupt c... | 08/19/2008 |
| 7379418 | Method for ensuring system serialization (quiesce) in a multi-processor environment A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies ... | 05/27/2008 |
| 7370193 | Computing system being able to quickly switch between an internal and an external networks and a method thereof The invention discloses a computing system such as a computer, a Personal Digital Assistant, or a mobile phone, being connected both to an internal network and an external network and being able to quickly and safely switch therebetween without being shut down while... | 05/06/2008 |
| 7369256 | Interruption of job in information processing apparatus by means of acquisition and release of resources An information processing apparatus, which attends to inputting and outputting of image data, and processes the image data by performing a job that uses a resource, includes a time-division resource allocation unit which performs the job by consecutively performing ... | 05/06/2008 |
| 7363407 | Concurrent arbitration of multidimensional requests for interrupt resources The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an in... | 04/22/2008 |
| 7356673 | System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second instruction set in a plurality of buffers proximate to a plurality of exe... | 04/08/2008 |
| 7356359 | Device detection in a mobile communication terminal A method for determining connection of an external device to a mobile communication terminal is provided. The method comprises detecting connection of an external device to a mobile communication terminal based on a signal generated by a first operation module of th... | 04/08/2008 |
| 7350005 | Handling interrupts in a system having multiple data processing units An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request having an associated priority level. The interrupt controller comprises... | 03/25/2008 |
| 7350006 | System and method of interrupt handling A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least importa... | 03/25/2008 |
| 7340547 | Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an ... | 03/04/2008 |
| 7337254 | Information processing system and method of controlling the same An information processing system operating in response to a remote control signal transmitted from a remote controller, the information processing system including a remote signal receiver to receive the remote control signal; an interrupt generator to generate a sy... | 02/26/2008 |
| 7328294 | Methods and apparatus for distributing interrupts The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and peripheral interfaces. Interrupts and their associated characteristics a... | 02/05/2008 |
| 7328295 | Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated... | 02/05/2008 |
| 7324558 | Method and apparatus for controlling the timing of a communication device A system timer controls the timing at which a mobile communication device communicates with a base station. The system timer includes a sequencer that executes a set of instructions stored in a sequencer RAM thereby causing a set of control signals to be supplied to... | 01/29/2008 |
| 7321947 | Systems and methods for managing multiple hot plug operations A method for managing multiple hot plug operations in an information handling system is provided. An instruction for initiating a new hot plug operation is received, the new hot plug operation including one or more hot plug system management interrupts (SMIs). Anoth... | 01/22/2008 |
| 7318113 | System and method communication system for reading or writing data to register between external card connection device and host device This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card (1) and a host device (2) are connected with each other in acc... | 01/08/2008 |
| 7316017 | System and method for allocatiing communications to processors and rescheduling processes in a multiprocessor system In a multiprocessor system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment. The sy... | 01/01/2008 |
| 7310803 | Method and system for executing multiple tasks in a task set A method, system and computer readable storage medium for executing a set of tasks. The method includes selecting an incomplete task in the set and then either starting its execution (if it was not previously suspended) or resuming its execution (if it was previousl... | 12/18/2007 |
| 7305588 | Testing the interrupt sources of a microprocessor A method of testing the interrupt sources of a microprocessor having a number of interrupts which are each operable to execute an interrupt service routine when enabled, each interrupt having a default priority level and an associated memory, the interrupts having a... | 12/04/2007 |
| 7302277 | Mobile communication terminal equipped with user identification module and method of improving boot speed of the same Disclosed is a technology associated with booting up a mobile communication terminal equipped with a user identification module (UIM). A method of improving the boot speed of a mobile communication terminal equipped with a UIM according to the present inventi... | 11/27/2007 |
| 7281073 | Method for controlling interrupts and auxiliary control circuit An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt... | 10/09/2007 |
