Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 5630141 | Hierarchical apparatus and method for processing device interrupts in a computer system A method and apparatus for an innovative hardware independent interface to the external world. The interrupt services are part of an overall I/O model providing an object base I/O system that supports dynamic configuration of the system. The design of the... | 05/13/1997 |
| 5623603 | Method of transferring data at adjustable levels of priorities to provide optimum response to user demands A method for organizing frames of data into queues for prioritized transmission is disclosed. Frames in queues can be transmitted to the other computer systems, and the priority of transfer is set according to the type of data. The frame currently being v... | 04/22/1997 |
| 5623676 | Computer program product and program storage device for safing asynchronous interrupts Processing of an asynchronous signal directed to a thread comprising a software routine executing in a computer system such that data consistency is maintained is discussed. Such processing proceeds by determining whether the routine is signal safe such t... | 04/22/1997 |
| 5619706 | Method and apparatus for switching between interrupt delivery mechanisms within a multi-processor system A switching circuit and method for transparently switching between two interrupt delivery mechanisms; namely a first interrupt circuit and a second interrupt circuit. The first interrupt circuit is adapted to service an interrupt request upon detecting th... | 04/08/1997 |
| 5606703 | Interrupt protocol system and method using priority-arranged queues of interrupt status block control data structures A data processing system includes a software interrupt handler which controls performance of interrupt actions. The system further includes plural subsystems, each subsystem manifesting an interrupt request upon occurrence of an associated event. Hardware... | 02/25/1997 |
| 5584028 | Method and device for processing multiple, asynchronous interrupt signals A device and method for processing a plurality of asynchronous interrupt signals provided to respective primary registers. The first provided of the signals is stored in a primary register. The primary registers are then closed to subsequently provided si... | 12/10/1996 |
| 5561785 | System for allocating and returning storage and collecting garbage using subpool of available blocks A computer storage management system establishes a subpool of available blocks of one size from a multiplicity of different storage frames. The available blocks are queued in the subpool. A garbage collection routine periodically or occasionally determine... | 10/01/1996 |
| 5557744 | Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception ... | 09/17/1996 |
| 5542076 | Method and apparatus for adaptive interrupt servicing in data processing system A method and apparatus for adaptive interrupt servicing is disclosed. The number of interrupts occurring within a predetermined time period is counted and stored as a value in an interrupt counter. At the end of each interrupt service, the interrupt count... | 07/30/1996 |
| 5481726 | Information processing system having a plurality of processors An information processing system including processors, and an interrupt controller responsive to an interrupt request signal from the processors for executing an interrupt process control of processes carried out by the processors. The interrupt controlle... | 01/02/1996 |
| 5471620 | Data processor with means for separately receiving and processing different types of interrupts A data processor which is provided with a flag in a Processor Status Word (PSW) 116 for storing prohibiting/enabling status for receiving all of the interrupt requests, and in which the instruction execution control unit 114 controls so that the flag beco... | 11/28/1995 |
| 5459872 | Software control of hardware interruptions In a computer system including an interrupt processor for interrupting a program being processed by the computer system, a sub-system for processing interrupt requests to the interrupt processor. The sub-system comprises hardware circuit for generating ha... | 10/17/1995 |
| 5438677 | Mutual exclusion for computer system Method and apparatus of mutual exclusion for executing protected code in a computer system. If an interrupt occurs during the execution of protected code, then the computer system is reconfigured to exclude interrupts having a lower priority than the curr... | 08/01/1995 |
| 5437039 | Servicing transparent system interrupts and reducing interrupt latency A system management interrupt (SMI) handler comprising a plurality of service tasks is provided a computer system to service SMIs. The service tasks are executed interleavingly with normal execution. A SMI task queue is provided to queue incidences of the... | 07/25/1995 |
| 5325536 | Linking microprocessor interrupts arranged by processing requirements into separate queues into one interrupt processing routine for execution as one routine Multiple interrupt request data is stored in a queue and handled by a single interrupt sub-routine to provide a batch handling capability to maximize the interrupt handling efficiency of a microprocessor. Events are organized into groups having a common i... | 06/28/1994 |
| 5291608 | Display adapter event handler with rendering context manager A data processing system that executes a process and further includes the capability to provide an interrupt signal upon the occurrence of a predetermined event. An interrupt manager is provided that includes the capability to receive the interrupt signal... | 03/01/1994 |
| 5265257 | Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queuing disciplines A fast arbiter for handling a large number of types of resources with multiple instances of each type of resource is provided. During a first cycle a request logic circuit broadcasts a request for a preselected type of resource onto a broadcast medium. Du... | 11/23/1993 |
| 5251302 | Network interface board having memory mapped mailbox registers including alarm registers for storing prioritized alarm messages from programmable logic controllers A network interface board provides a communication link between a personal computer and a network bus connecting a plurality of programmable logic controllers. The network interface board mounts in an expansion slot of the personal computer. The programma... | 10/05/1993 |
| 5146595 | Grouping device for forming input signals into groups A grouping device comprises a register table and a grouping unit the register table having m registers corresponding to m groups, each register including an n-bits data storing portion corresponding to the n input signals, for registering relationships be... | 09/08/1992 |
| 5006982 | Method of increasing the bandwidth of a packet bus by reordering reply packets A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes requ... | 04/09/1991 |
| 5003464 | Methods and apparatus for efficient resource allocation A multiprocessor data processing system is described in which the function of coordinating the actions of all of the processors of the multiprocessor system can be assigned to any one of the processors of the system. In order to ensure assignment of the c... | 03/26/1991 |
| 4792890 | Method for resolving conflicts between interrupt sources sharing the same priority level A method for controlling a processor in a data processing system so that multiple events are serviced on a single interrupt level. On the occurrence of a first interrupt request the processor is forced to run the routine that services the interrupt in a b... | 12/20/1988 |
| 4764864 | Circuit arrangement capable of improving overhead of a control program on interrupting into a virtual machine In an arrangement for use in a virtual machine operable in accordance with a plurality of operating systems, hardware circuits, such as a judging circuit (36) and an interruption reception circuit (31), monitor reception of an interruption request and the... | 08/16/1988 |
| 4761732 | Interrupt controller arrangement for mutually exclusive interrupt signals in data processing systems An interrupt controller circuit arrangement is used for encoding and storing "interrupt" signals indicating random (asynchronous) occurrence of corresponding events and for delivering corresponding "interrupt" (alarm command) signals to a (synchronous) mi... | 08/02/1988 |
| 4740915 | Method of controlling a microprocessor to monitor input signals at irregular mutually intersecting intervals Control of a microcomputer performing a wide variety of functions in a motor vehicle in which the sequences of input and output signals intersect in time, instead of being performed by an elaborate input/output unit, is performed in the microcomputer itse... | 04/26/1988 |
| 4644465 | Apparatus for controlling I/O interrupt in multiprocessor system An apparatus for controlling interrupts is provided in a system controller SC of a multiprocessor system in which a plurality of instruction processors IP share a main storage MS and a channel controller CHC through the system controller SC. The apparatus... | 02/17/1987 |
| 4023143 | Fixed priority interrupt control circuit An apparatus for controlling the transmission of multiple level priority interrupt signals to a central processing unit. A number of storage elements are responsive to the interrupt signals on an individual basis. A last-in first-out memory having an outp... | 05/10/1977 |
| 4010450 | Fail soft memory A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory mo... | 03/01/1977 |
