Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 7596648 | System and method for information handling system error recovery An information handling system recovers from memory errors associated with a memory unit that supports operation of an SMI handler by using another memory unit to support operation of the SMI handler. For example, if an SMI handler detects an error associated with a... | 09/29/2009 |
| 7584316 | Packet manager interrupt mapper A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about system-related functions for a plurality of channels. Using status regis... | 09/01/2009 |
| 7529876 | Tag allocation method Embodiments of the present invention provide methods and systems for allocating multiple tags to multiple requesters in back to back clock cycles. A tag pool may be divided into a predetermined number of sections. Each requester may be associated with at least one o... | 05/05/2009 |
| 7478186 | Interrupt coalescer for DMA channel A DMA interrupt coalescer processes interrupts received from a DMA channel of a DMA controller by transmitting an interrupt request to an interrupt controller if a coalescing condition is satisfied after receiving one or more delayable interrupts, or transmitting th... | 01/13/2009 |
| 7464210 | Data processing system having a data transfer unit for converting an integer into a floating-point number when tranferring data from a peripheral circuit to a memory This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same interrupt exception handling routine if the request event occurs a plura... | 12/09/2008 |
| 7444451 | Adaptive interrupts coalescing system with recognizing minimum delay packets The present invention relates to an adaptive interrupts coalescing system with recognizing minimum delay packets. The adaptive interrupts coalescing system of the invention comprises a first calculating device, a packet header parser, a second calculating device, an... | 10/28/2008 |
| 7415561 | Computer for dynamically determining interrupt delay In a computer having a unit for outputting an interrupt request to a processor, a delay condition from occurrence of an interrupt event to issue of an interrupt request to the processor can be dynamically determined depending on the processor load status, etc. The i... | 08/19/2008 |
| 7400685 | Decoding method and apparatus and recording method and apparatus for moving picture data A method and apparatus for recording moving picture data encoded using a prediction encoding system, in which the playback control information is recorded along with moving picture data encoded using the MPEG system. The playback control information includes the inf... | 07/15/2008 |
| 7366813 | Event queue in a logical partition An information processing system is provided which includes a plurality of system resources, and an event queue having a predetermined number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events i... | 04/29/2008 |
| 7366814 | Heterogeneous multiprocessor system and OS configuration method thereof Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt... | 04/29/2008 |
| 7366799 | Document processing system including multi-device compatible interface and related methods A document processing system may include a document processing device (e.g., a copier), a host (e.g., a computer server), and a multi-device compatible interface for enabling operation of the host and the document processing device from among a plurality of differen... | 04/29/2008 |
| 7363412 | Interrupting a microprocessor after a data transmission is complete A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives ... | 04/22/2008 |
| 7363407 | Concurrent arbitration of multidimensional requests for interrupt resources The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an in... | 04/22/2008 |
| 7363410 | Flexible interrupt handling methods for optical network apparatuses with multiple multi-protocol optical networking modules An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers to handle interrupts triggered by the function blocks of multi-protocol... | 04/22/2008 |
| 7352864 | Display device A display device comprises a nonvolatile memory for storing an amount of adjustment obtained in a blanking adjustment most recently performed for a particular video signal, means for judging whether or not the particular video signal is inputted, means for masking a... | 04/01/2008 |
| 7350006 | System and method of interrupt handling A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least importa... | 03/25/2008 |
| 7343004 | Numeric and text paging with an integral PLC modem At least one exemplary embodiment of the present invention includes a method comprising formatting a message at a first modem integral to a first programmable logic controller, and transmitting the formatted message from the first modem via a communications network.... | 03/11/2008 |
| 7340547 | Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an ... | 03/04/2008 |
| 7337190 | Apparatus and method for hardware-based file system A hardware-based file system includes multiple linked sub-modules that perform functions ancillary to client data handling. Each sub-module is associated with a metadata cache. A doubly-rooted structure is used to store each file system object at successive checkpoi... | 02/26/2008 |
| 7330877 | Devices, softwares and methods for rescheduling multi-party sessions upon premature termination of session Devices, softwares and methods reschedule multi-party sessions upon premature termination of a wireless communication session. Upon sensing a premature termination, an access point transmits a rescheduling frame. All sessions are advanced in time, which saves time i... | 02/12/2008 |
| 7328296 | Interrupt processing system An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to di... | 02/05/2008 |
| 7328294 | Methods and apparatus for distributing interrupts The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and peripheral interfaces. Interrupts and their associated characteristics a... | 02/05/2008 |
| 7321945 | Interrupt control device sending data to a processor at an optimized time An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt issuing unit for issuing interrupts to the CPU. The interrupt issuing unit i... | 01/22/2008 |
| 7318102 | Reliable datagram A reliable datagram service is implemented with a source and destination resource (SDR). Source SDR resources, at a source device, multiplex units of work produced by at least one source application instance (AI) into a serial unit of work stream having units of wor... | 01/08/2008 |
| 7310689 | Bypassing disk I/O operations when porting a computer application from one operating system to a different operating system Systems, methods, and computer products that improve the performance of computer-implemented I/O operations for complex applications, such as a database, that are ported to target computer systems that are not tailored to support the high-performance services that m... | 12/18/2007 |
| 7302512 | Interrupt steering in computing devices to effectuate peer-to-peer communications between device controllers and coprocessors A computer device, an input/output (“I/O”) communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications between a device controller and a coprocessor. Advantageously, the vario... | 11/27/2007 |
| 7289964 | System and method for transaction services patterns in a netcentric environment The present disclosure provides for implementing transaction services patterns. Logical requests are batched for reducing network traffic. A batched request is allowed to indicate that it depends on the response to another request. A single message is sent to all ob... | 10/30/2007 |
| 7290077 | Event queue structure and method An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the ... | 10/30/2007 |
| 7287111 | Method and system for creating and dynamically selecting an arbiter design in a data processing system A method, system and computer program product for creating and dynamically selecting an arbiter design within a data processing system on the basis of command history is disclosed. The method includes selecting a first arbiter for current use in arbitrating between ... | 10/23/2007 |
| 7281073 | Method for controlling interrupts and auxiliary control circuit An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt... | 10/09/2007 |
| 7281121 | Pipeline processing device and interrupt processing method At an MA stage, data, such as a header address of an interrupt processing routine, is loaded via a data bus and immediately supplied to a program counter via multiplexers without the intervention of an instruction decode stage in accordance with a setting address ou... | 10/09/2007 |
| 7274368 | System method and computer program product for remote graphics processing A system, method, and computer program product are provided for remote rendering of computer graphics. The system includes a graphics application program resident at a remote server. The graphics application is invoked by a user or process located at a client. The i... | 09/25/2007 |
| 7263568 | Interrupt system using event data structures Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in resp... | 08/28/2007 |
| 7260663 | System and method for presenting interrupts An information processing system is provided which includes an interrupt table including a plurality of entries relating to interrupts requested by entries in a plurality of event queues. The entries of the interrupt table reference identifiers, and the identifiers ... | 08/21/2007 |
| 7260662 | I2C bus controlling method A module has an IC for communication control (a PHY unit) and an EEPROM (or MCU) connected to the PHY unit via an I2C bus. When a software reset is triggered while the PHY unit reads non-volatile register (NVR) data from the EEPROM (or MCU) via the I2C bus, the modu... | 08/21/2007 |
| 7254726 | System and method for managing system events by creating virtual events in an information handling system In a computer system or information handling system, a virtual system event provides for the communication of the notification of a system events from the hardware of the computer system to the power and configuration management system of the computer system. ... | 08/07/2007 |
| 7245627 | Sharing a network interface card among multiple hosts A network interface device includes a fabric interface, adapted to exchange messages over a switch fabric with a plurality of host processors, the messages containing data, and a network interface, including one or more ports adapted to be coupled to a network exter... | 07/17/2007 |
| 7236987 | Systems and methods for providing a storage virtualization environment A storage virtualization environment is provided that includes a system for providing one or more virtual volumes. The system may include a host system and a set of storage devices, each of which includes physical block addresses that stores data. Further, the syste... | 06/26/2007 |
| 7234004 | Method, apparatus and program product for low latency I/O adapter queuing in a computer system In a computer system, an I/O adapter comprises at least one I/O request mailbox for receiving I/O requests and data from a CPU. The mailbox is connected to at least one I/O request queue storage for storing a plurality of I/O requests and related data or main memory... | 06/19/2007 |
| 7222251 | Microprocessor idle mode management system An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock ... | 05/22/2007 |