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| Number | Title | Issue Date |
| 8180943 | Method and apparatus for latency based thread scheduling A method and apparatus for providing latency based thread scheduling. A thread attribute, e.g., latency of a process, is used in effecting the scheduling of the thread. ... | 05/15/2012 |
| 8069291 | Method and computer program product for event detection A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, sta... | 11/29/2011 |
| 8015337 | Power efficient interrupt detection Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor. The interrupt request detection circuitry comprises: an interrupt signal input for receiving an interrupt signal; an input for receiving a signal from ... | 09/06/2011 |
| 7882293 | Interrupt masking control A processor core 4 is provided with an interrupt controller 22 which serves to set an interrupt mask bit F and a hardware control when an interrupt fiq occurs. A masking control signal NMI serves to either allow or prevent the software clearing of the ... | 02/01/2011 |
| 7853744 | Handling interrupts when virtual machines have direct access to a hardware device In virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system and has direct access to a hardware device coupled to the virtualized computer system via a communication interface, a computer-implemented me... | 12/14/2010 |
| 7849246 | I2C bus control circuit An I2C bus control circuit includes a continuous transmission control section in addition to a transmission control section, a sequence control section, a data line control section, and a clock line control section. The continuous transmission control section has a ... | 12/07/2010 |
| 7805556 | Interrupt control apparatus, bus bridge, bus switch, image processing apparatus, and interrupt control method An interrupt control apparatus that controls an interrupt process request caused by a predetermined interrupt factor is disclosed. The interrupt control apparatus includes: an obtaining unit configured to obtain an interrupt process request signal including an inter... | 09/28/2010 |
| 7788434 | Interrupt controller handling interrupts with and without coalescing An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt ... | 08/31/2010 |
| 7779191 | Platform-based idle-time processing A system and method for transitions a computing system between operating modes that have different power consumption characteristics. When a system management unit (SMU) determines that the computing system is in a low activity state, the SMU transitions the central... | 08/17/2010 |
| 7725636 | Trigger core A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, sta... | 05/25/2010 |
| 7707343 | Interrupt control circuit and method According to an embodiment of the present invention, an interrupt control circuit that controls a plurality of interrupt requests for interrupt handling executed by a processor, includes: an interrupt control module unit as a detecting unit determining whether or no... | 04/27/2010 |
| 7702836 | Parallel processing device and exclusive control method To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which... | 04/20/2010 |
| 7673088 | Multi-tasking interference model The subject disclosure pertains to a multi-tasking interference system. A gatekeeper receives primary and secondary inputs, and a quantifier ascertains attention values associated with primary inputs and interruption values associated with secondary inputs. Attentio... | 03/02/2010 |
| 7668998 | Methods, systems, and devices for providing an interrupt scheme in automated pharmaceutical dispensing machines without centralized arbitration In a method for communication between a master node and a plurality of slave nodes connected by a bus therebetween, a first interrupt request is asserted by one of the plurality of slave nodes via a primary interrupt line. The plurality of slave nodes are electrical... | 02/23/2010 |
| 7549005 | System and method for managing interrupts Method and system for managing interrupts originating from multiple sources is provided. The method includes assigning interrupt sources to a group; notifying an adapter of interrupt groups; identifying each interrupt group; writing a first interrupt to an interrupt... | 06/16/2009 |
| 7500039 | Method for communicating with a processor event facility A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor... | 03/03/2009 |
| 7478185 | Directly initiating by external adapters the setting of interruption initiatives The setting of interruption initiatives is directly initiated by external adapters. An adapter external to the processors at which the initiative is to be made pending sends a request directly to a system controller coupled to the adapter and the processors. The sys... | 01/13/2009 |
| 7426728 | Reducing latency, when accessing task priority levels One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt ... | 09/16/2008 |
| 7423565 | Apparatus and method for comparison of a plurality of analog signals with selected signals In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In making a comparison with a predetermined value, a second buffer/register stores either a preselected valu... | 09/09/2008 |
| 7421521 | System, method and device for real time control of processor A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may, for example, be indicated by a signal from, for example, a slot timer,... | 09/02/2008 |
| 7398343 | Interrupt processing system An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to di... | 07/08/2008 |
| 7386647 | System and method for processing an interrupt in a processor supporting multithread execution A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to the read-only portion of system memory. Upon receipt of an interrupt, ... | 06/10/2008 |
| 7380063 | Cache flushing Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flu... | 05/27/2008 |
| 7380041 | Managing input/output interruptions in non-dedicated interruption hardware environments Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. Th... | 05/27/2008 |
| 7366987 | Interrupt processing in display control The present invention provides a display control system suitable to flexible and smooth presentation. The invention can include a projector that stores page data included in projector display data in a stack area by a stack system in which the page data correspondin... | 04/29/2008 |
| 7363407 | Concurrent arbitration of multidimensional requests for interrupt resources The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an in... | 04/22/2008 |
| 7363412 | Interrupting a microprocessor after a data transmission is complete A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives ... | 04/22/2008 |
| 7360117 | In-circuit emulation debugger and method of operation thereof An in-circuit emulation debugger and method of operating an in-circuit emulation debugger to test a digital signal processor (DSP). In one embodiment, the in-circuit emulation debugger includes: (1) a device emulation unit, coupled to a collocated DSP core, for emul... | 04/15/2008 |
| 7356817 | Real-time scheduling of virtual machines A method for scheduling a plurality of virtual machines includes: determining a resource requirement (Xi) for each virtual machine (VM); determining an interrupt period (Yi) for each VM; and scheduling the plurality of VMs based, at least in pa... | 04/08/2008 |
| 7353312 | Method and apparatus for detecting conditions for blocking a CPU's receipt of signals returned from a peripheral device A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU, wherein the return signal is a signal transmitted by a system chip in r... | 04/01/2008 |
| 7351151 | Gaming board set and gaming kernel for game cabinets The present invention is a method and apparatus enabling a low cost hardware upgrade path and low cost processor board retrofit for gaming machines. The enabling features include a two-board set made up of an industry standard form factor processor board (a single b... | 04/01/2008 |
| 7353370 | Method and apparatus for processing an event occurrence within a multithreaded processor A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a fir... | 04/01/2008 |
| 7353163 | Exception handling method and apparatus for use in program code conversion A method of handling exceptions for use in an emulator (20) performing program code conversion. Registers (X) of a subject machine (11) being emulated (20) are represented by a pair of abstract registers (XA,XB) on the targ... | 04/01/2008 |
| 7350005 | Handling interrupts in a system having multiple data processing units An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request having an associated priority level. The interrupt controller comprises... | 03/25/2008 |
| 7350007 | Time-interval-based system and method to determine if a device error rate equals or exceeds a threshold error rate An apparatus and method to determine if a device error rate equals or exceeds a threshold. In an apparatus embodiment, a system comprises a device, and an interrupt handler executable by a processor. The interrupt handler executes, upon expiration of a time period, ... | 03/25/2008 |
| 7340547 | Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an ... | 03/04/2008 |
| 7330999 | Network storage appliance with integrated redundant servers and storage controllers A network storage appliance integrates a plurality of servers and a plurality of storage controllers into a single chassis. The storage controllers control transfers of data between the servers and storage devices controlled by the storage controllers. The servers a... | 02/12/2008 |
| 7328296 | Interrupt processing system An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to di... | 02/05/2008 |
| 7328295 | Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated... | 02/05/2008 |
| 7325084 | Messages signaling interrupt (MSI) processing system An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to di... | 01/29/2008 |
