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| Number | Title | Issue Date |
| 7177963 | System and method for low-overhead monitoring of transmit queue empty status A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of transmit status or excessive interrupt servicing. The queue monitoring ... | 02/13/2007 |
| 7177943 | System and method for processing packets in a multi-processor environment A method for processing packets in a multi-processor environment, that includes receiving a set-up request packet for a communication session and directing the set-up request packet to a selected one of a plurality of processors. A set-up reply packet is generated a... | 02/13/2007 |
| 7177960 | Mobile terminal To display a horizontally oblong movie on a vertically oblong display portion, the movie may be displayed with being rotated 90 degrees by a CPU while the display portion is held in an orientation where the display portion is wider than tall. Since this arrangement ... | 02/13/2007 |
| 7177925 | Event management system One embodiment of an event management system, operating on a computer system having event producers and event consumers, includes an initial event handler program and an event queue having a first event. The initial event handler program retrieves the first event fr... | 02/13/2007 |
| 7174472 | Low overhead integrated circuit power down and restart An integrated circuit provided with a power down and power up mechanism which operates by storing state data including at least architectural state data within storage cells having their own power supply with the main power supply being removed during the power down... | 02/06/2007 |
| 7174554 | Tools and methods for discovering race condition errors Tools and methods are described herein for discovering race condition errors in a software program. The errors are discovered by deliberately causing a processor executing the test program to switch threads at intervals other than normally scheduled by an operating ... | 02/06/2007 |
| 7174393 | TCP/IP offload network interface device A system for protocol processing in a computer network has a TCP/IP Offload Network Interface Device (TONID) associated with a host computer. The TONID provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating da... | 02/06/2007 |
| 7174352 | File system image transfer The invention provides a method and system for duplicating all or part of a file system while maintaining consistent copies of the file system. The file server maintains a set of snapshots, each indicating a set of storage blocks making up a consistent copy of the f... | 02/06/2007 |
| 7171501 | System and method for asynchronous transfer of control An invention is provided for a synchronous transfer of control. An asynchronous interrupt exception is received, and in response, the value of a reference counter is determined. The value of the reference counter is based on the execution of synchronized code. Gener... | 01/30/2007 |
| 7171509 | Method and apparatus for host messaging unit for Peripheral Component Interconnect busmaster devices Peripheral Component Interconnect (PCI) device contains Host Messaging Unit (HMU) which is operative to off load host processor and PCI device processor from PCI bus transfer overhead. HMU is configurable to asynchronously retrieve host processor commands from circu... | 01/30/2007 |
| 7171531 | Process job flow analysis A storage device is configured with one or more processes that receive, process, and pass on jobs from a source. The number of jobs received by a process is compared with the number of jobs completed and/or passed on by the process. If the number of jobs that are re... | 01/30/2007 |
| 7171547 | Method and apparatus to save processor architectural state for later process resumption A method and an apparatus for restoring logic states using programming code are disclosed. In one embodiment, the process of a data processing system identifies a first logic value stored in a first register and branches to a first location within the programming co... | 01/30/2007 |
| 7168075 | Automation device and updating method A device used for control or monitoring of a process is updated without interruption or exceeding upper response time limits for response to a change in the state of the process. If the updating task requires too much run time, the updating task is terminated. As so... | 01/23/2007 |
| 7167982 | Securing decrypted files in a shared environment A method, system and computer program product for securing decrypted files in a shared environment. A filter driver in a kernel space may be configured to control service requests to encrypted files stored in a shared area, e.g., a shared directory on a disk unit, a... | 01/23/2007 |
| 7167939 | Asynchronous system bus adapter for a computer system having a hierarchical bus structure A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system bus adapter which includes a local bus adapter for handling transacti... | 01/23/2007 |
| 7167814 | Analysis system for analyzing the condition of a machine An apparatus for analyzing the condition of a machine, comprising: at least one input for receiving measurement data from a sensor for surveying a measuring point of the machine; data processing means for processing condition data dependent on said measurement data;... | 01/23/2007 |
| 7167927 | TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanism A network interface device has a fast-path ACK generating and transmitting mechanism. ACKs are generated using a finite state machine (FSM). The FSM retrieves a template header and fills in TCP and IP fields in the template. The FSM is not a stack, but rather fills ... | 01/23/2007 |
| 7167893 | Methods and systems for processing a plurality of errors As part of handling a large amount of error information generated on a mainframe system associated, for example, with a telephone billing system, a utility software program allows a user to easily process the error information. The information is generated by the ma... | 01/23/2007 |
| 7165135 | Method and apparatus for controlling interrupts in a secure execution mode-capable processor A method is provided for controlling interrupts in a secure execution mode-capable processor. The method includes detecting an interrupt and performing a predetermined routine in response to detecting the interrupt. The method further includes performing a second ro... | 01/16/2007 |
| 7165134 | System for selectively generating real-time interrupts and selectively processing associated data when it has higher priority than currently executing non-real-time operation A method is disclosed. The method includes receiving real-time data at a personal computer implementing a general purpose operating system, generating a real-time event at the personal computer and determining whether the real-time event has a higher priority than a... | 01/16/2007 |
| 7165183 | Temperature controlled semiconductor circuit An interrupt signal EMG is put out to a microprocessor 10 when a thermal monitor 40 detects that a package temperature exceeds a reference. The microprocessor then increases a frequency division value N stored in a frequency division value register ... | 01/16/2007 |
| 7165128 | Multifunctional I/O organizer unit for multiprocessor multimedia chips An apparatus and method for providing enhanced performance for multi-processor multimedia chips. In one embodiment, the present invention is comprised of a data and communication apparatus coupled with the multimedia system in which the multi-processor multimedia ch... | 01/16/2007 |
| 7164610 | Microcomputer having a flush memory that can be temporarily interrupted during an erase process A microcomputer with a built-in non-volatile semiconductor memory, which can automatically perform a work of temporarily interrupting automatic writing or automatic erase and accepting an interruption process when an interruption occurs during the automatic writing ... | 01/16/2007 |
| 7162560 | Partitionable multiprocessor system having programmable interrupt controllers A system that may optionally be partitioned into multiple domains is disclosed. Each domain is capable of independently powering on, executing a firmware program, and loading an operating system, including a legacy operating system, as well as running an application... | 01/09/2007 |
| 7162558 | Interrupt signal processing circuit for sending interrupt requests to a computer system A computer system associated with a plurality of interrupt sources that produce interrupt signals may include interrupt signal processing blocks corresponding to the interrupt sources, respectively. Each of the interrupt processing blocks can include: a counter for ... | 01/09/2007 |
| 7162559 | System for controlling interrupts between input/output devices and central processing units An interrupt controller enables multiple CPUs to control access to an increased number of interrupts. Each of a plurality of CPUs is able to block interrupts written to the interrupt controller at multiple levels. First, each CPU is able to block interrupts at the i... | 01/09/2007 |
| 7159057 | Evaluation chip An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20-1 to 2-4 perform a logical operation on a plurality of signals S11 to S14 ... | 01/02/2007 |
| 7155718 | Method and apparatus to suspend and resume on next instruction for a microcontroller In a computer system including at least one microcontroller, by suspending tasks after execution of particular instructions, such as a load-register-from-external-memory instruction, or when a resource is not ready, unnecessary attempts to execute subsequent instruc... | 12/26/2006 |
| 7152169 | Method for providing power management on multi-threaded processor by using SMM mode to place a physical processor into lower power state A power management technique uses system management interrupt (SMI) to manage states of a processor that includes multiple logical processors. When the SMI is generated, the states of logical processors are verified. When all of the logical processors are idle, the ... | 12/19/2006 |
| 7152125 | Dynamic master/slave configuration for multiple expansion modules A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of th... | 12/19/2006 |
| 7149854 | External locking mechanism for personal computer memory locations A method and system for providing an external locking mechanism for memory locations. The memory includes a first plurality of storage locations configured with BIOS data and a second plurality of storage locations. The second plurality of storage locations includes... | 12/12/2006 |
| 7149838 | Method and apparatus for configuring multiple segment wired-AND bus systems A special bus master, called a configuration host, “walks” a bus system to discover the bus topology and bus bridges that form that topology. Once the bridges have been located, the configuration host assigns a bridge ID to each bridge and enters information int... | 12/12/2006 |
| 7149831 | Batch processing of interrupts A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working list of working interrupt vectors. The method also includes performin... | 12/12/2006 |
| 7149872 | System and method for identifying TLB entries associated with a physical address of a specified range A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB e... | 12/12/2006 |
| 7149851 | Method and system for conservatively managing store capacity available to a processor issuing stores Method and system for conservatively managing store capacity available to a processor issuing stores are provided and described. In particular, a counter mechanism is utilized, whereas the counter mechanism is incremented or decremented based on the occurrence of pa... | 12/12/2006 |
| 7149830 | Semiconductor device and microcontroller A semiconductor device in which input terminals for external interrupts can be set as desired. A plurality of external input terminals can be specified as interrupt terminals which output an input signal to an external interrupt circuit via an interrupt terminal sel... | 12/12/2006 |
| 7150018 | Method and system for deterministic ordering of software modules A method and system for ordering software modules in a guaranteed order for execution. Unique values are statically assigned to software modules (e.g., filter drivers) when fully developed. Each module's assigned value determines its relative position to other modul... | 12/12/2006 |
| 7146232 | Agent program environment A system and method for programming a plurality of agents onto a distributed control system are disclosed. The system includes a terminal that displays a graphical user interface having a plurality of images. The plurality of images includes a first image showing a ... | 12/05/2006 |
| 7146482 | Memory mapped input/output emulation A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address space of a machine associated with a first adapter to allocate a resou... | 12/05/2006 |
| 7145913 | Thread based scalable routing for an active router In the present scalable system routing method, received packets are associating with threads for processing the received packets. While a previously received packet is being processed, arrival of an interrupt is checked. If there is an interrupt, a thread is created... | 12/05/2006 |
