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| Number | Title | Issue Date |
| 4638432 | Apparatus for controlling the transfer of interrupt signals in data processors To ensure security of interrupt input signals to a computer system (30-3N) with minimum interruption of the running of programs in the system, two interrupt logic units (1) receive interrupt signals on leads (20-2x) from connected apparatus and store flag... | 01/20/1987 |
| 4630041 | Enhanced reliability interrupt control apparatus Interrupt control apparatus in a data processing system for acknowledging on a priority basis one among several possible asynchronous interruptions (INT1, INTN), such apparatus comprising a priority network (5), a latching (7) and a validation circuit (11... | 12/16/1986 |
| 4601008 | Data processing system A data processing system having a performance measurement system which is capable of setting desired performance measurement items. In the performance measuring system an interrupt by internal timer is used for triggering performance measurement, the perf... | 07/15/1986 |
| 4591975 | Data processing system having dual processors A data processing system having a host processor and an attached processor is disclosed. Each processor is capable of executing user programs under a different operating system and each processor is capable of accessing system memory but the host processo... | 05/27/1986 |
| 4584644 | Method of controlling use of resources in a data processing system by at least two processes A data processing system in which a process having a low priority may be interrupted by a process having a higher priority and in which an interrupted process ceases its current operation immediately the interrupt occurs, a mechanism by which the higher p... | 04/22/1986 |
| 4575817 | Switching of programming routine supporting storage stacks A system in which a device or machine is controlled by instructions from a data processor is provided which minimizes main memory storage requirements. An interrupt service routine monitors the input to the processor received from the device in response t... | 03/11/1986 |
| 4541047 | Pipelined data processing system A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit for operating all instructions to be executed by the data processing unit, a first group of general purpose registers for sto... | 09/10/1985 |
| 4519032 | Memory management arrangement for microprocessor systems A memory management system is structured for use with a self-contained microprocessor to form a multi-user computer. The system operates to establish user and kernel modes each having different operating permissions. When the system is operating in the us... | 05/21/1985 |
| 4504903 | Central processor with means for suspending instruction operations A central processor for use in a data processing system that is adapted for processing sequences of characters. Information identifying a string of characters to be examined, including an initial memory location of the first character in the sequence and ... | 03/12/1985 |
| 4494189 | Method and means for switching system control of CPUs The embodiment obtains rapid switching between system control programs (SCPs) by switching an address in a prefix register in a CPU of a MP or UP data processing system from a guest SCP's PSA (program save area) to a host SCP's PSA by fetching the host pr... | 01/15/1985 |
| 4485440 | Central processor utilization monitor Data relative to code instruction use of a central processor unit (CPU) is collected by accumulating counts of code instructions to be executed upon termination of a clock interrupt process over a predetermined interval. Information stored on occurrence o... | 11/27/1984 |
| 4451898 | Asynchronous interface message transmission using source and receive devices An asynchronous interface enables the transfer of information between a set of devices operating in a loop and having a wide range of operating speeds. Each device can enter a Controller active state in which it sources command frames to control the loop ... | 05/29/1984 |
| 4450525 | Control unit for a functional processor A control unit for a functional processor is disclosed which minimizes programming complexity by eliminating data transfers and the transfer control associated with two level memory systems and which improves flexibility in program task changeovers in pip... | 05/22/1984 |
| 4441154 | Self-emulator microcomputer An electronic digital processor system including an internal memory, an arithmetic and logic unit, registers, peripheral control circuitry providing an internal mode, an external mode, emulator mode, data paths, and control and timing circuitry. In the in... | 04/03/1984 |
| 4434461 | Microprocessor with duplicate registers for processing interrupts A unique microprocessor for controlling portable and mobile cellular radiotelephones is architectured to process high speed supervisory signalling, while also minimizing power drain. The architecture of the microprocessor is organized around three buses, ... | 02/28/1984 |
| 4425630 | Sequence instruction display system A sequence instruction display system used with a programmable sequence controller for displaying a desired sequence instruction and the on-off state of the input or output element corresponding thereto. A data processor stores the address data of an inpu... | 01/10/1984 |
| 4422142 | System for controlling a plurality of microprocessors A system for controlling a plurality of microprocessors, comprising a common memory which can be selectively switched to exclusive buses which are connected to the plurality of microprocessors, respectively, and a priority control circuit which determines... | 12/20/1983 |
| 4414664 | Wait circuitry for interfacing between field maintenance processor and device specific adaptor circuit A field maintenance processor including a microprocessor that effects transparent refreshing of a dynamic memory includes a counter circuit which times the duration of the "wait" signal produced by a slow memory or a slow peripheral device accessed by the... | 11/08/1983 |
| 4403300 | Method and system of operation of an addressable memory permitting the identification of particular addresses The invention relates to data processing systems which make use of an addressable memory. It proposes a method and a system of operation which permits one to particularize or mark for future reference, as desired, certain addresses in the addressable memo... | 09/06/1983 |
| 4396915 | Automatic meter reading and control system A remote automatic utility reading system includes a reading control center for transmitting commands to and receiving measurement data from remote terminal units via a command responsive control unit. The control unit is characterized by a computer havin... | 08/02/1983 |
| 4336588 | Communication line status scan technique for a communications processing system A communication processor is coupled to recognize and handle on a priority basis, service interrupt requests from a plurality of communication line adapters. The processor is also adapted to perform a firmware-controlled scan of the communication line ada... | 06/22/1982 |
| 4271464 | Switching arrangement for the input of interrupt commands and the output of interrupt acknowledgment for computer systems In order to provide an interrupt command signal in a computer and receive an interrupt acknowledgment at a single input/output terminal, an interrupt command encoder includes an inverter for receiving an interrupt command at a first logic level and provid... | 06/02/1981 |
| 4259717 | Information processor An information processor is comprised of a plurality of circuits each of which is controlled by firmware and connected to a common bus and has a contention circuit for the bus. An arithmetic control unit for controlling the execution of the firmware is pr... | 03/31/1981 |
| 4251858 | Paging, status monitoring and report compiling system for support, maintenance and management of operator-supervised automatic industrial machines A distributed microcomputer network is interconnected with a plurality of operator-supervised, numerically controlled (N/C) machines, visual display paging boards, terminal printers and CRT/keyboard terminals for communicating operator-originated CALLs (r... | 02/17/1981 |
| 4251866 | Control unit having a memory in which a program consisting of command words is stored A control unit contains a memory in which a program having command words is stored, a condition multiplexer with which it is determined whether a condition indicated in a command word exists, and an address unit in which the actual address of the command ... | 02/17/1981 |
| 4236203 | System providing multiple fetch bus cycle operation In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generate... | 11/25/1980 |
| 4196470 | Method and arrangement for transfer of data information to two parallelly working computer means Data information units are registered sequentially preparatory for transfer to two computer means, each by parallel-synchronous cooperation executing one of two accordant instruction sequences. The execution of each instruction sequence is divided in numb... | 04/01/1980 |
| 4193113 | Keyboard interrupt method and apparatus A method for interrupting the execution of a keyboard macroinstruction by a central processor to permit execution of non-keyboard macroinstructions when no external data is present in the central processor keyboard buffer. Auxiliary registers are provided... | 03/11/1980 |
| 4183083 | Method of operating a multiprogrammed computing system A unique method of operating a multiprogrammed computing system by dynamically regulating central processing unit (CPU) and/or peripheral resource access such that the parallel processing capability, i.e., thruput of the computing system, is increased and... | 01/08/1980 |
| 4161787 | Programmable timer module coupled to microprocessor system A programmable timer module (PTM) is provided as a component of a microprocessor system in order to generate and measure varying time intervals under program control. The programmable timer module includes, in one embodiment, three independent 16-bit time... | 07/17/1979 |
| 4129901 | Plural-sequence control system A sequence control system is disclosed which is suitable for control of plural objects to at least some of which similar control sequence operations are performed. In addition to a logical operation unit for receiving signals representative of states of t... | 12/12/1978 |
| 4068297 | Numerical control system A numerical control system for controlling a machine tool includes a central processing unit, a first memory for storing a first control program, a second memory for storing a second control program, and a third memory for temporarily storing data. Each o... | 01/10/1978 |
| 3999169 | Real time control for digital computer utilizing real time clock resident in the central processor The proposed real time clock control of a computer system is implemented as programmer's working register in the central processing unit, instead of as an auxiliary subsystem in the input-output logic. Implemented in this manner, the real time clock is mo... | 12/21/1976 |
| 3974480 | Data processing system, specially for real-time applications This invention relates to a data processing system, specially for real-time applications. This system comprises a processor having a relatively small number of registers, and safeguard storages consisting each of a stack of sequentially addressable regist... | 08/10/1976 |
