Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 7398378 | Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an in... | 07/08/2008 |
| 7395362 | Method for a slave device to convey an interrupt and interrupt source information to a master device A computer system, more generally a master-slave system, may be configured with interrupt handling capability without additional dedicated interrupt lines. An interrupt condition may be bound with its relevant cause information and transmitted by a slave device duri... | 07/01/2008 |
| 7395434 | Method for secure storage and verification of the administrator, power-on password and configuration information A computer includes a processor, an input device and a read only memory (“ROM”). One or more passwords are flashed in the ROM in encoded form. The encoding process may include any well-known encryption or hash process. The password may include a power-on passwor... | 07/01/2008 |
| 7389368 | Inter-DSP signaling in a multiple DSP environment The invention includes a method and apparatus for synchronizing a first processor with a second processor. The method includes storing in a register parallel bits of data from the first processor, wherein at least one bit of data is a logic ONE. An output signal is ... | 06/17/2008 |
| 7389496 | Condition management system and a method of operation thereof For use with a processor employing a hierarchical register consolidation structure (HRCS), a condition management system and method of operation thereof. In one embodiment, the system includes a condition management structure (CMS) that abstracts groups of status in... | 06/17/2008 |
| 7386640 | Method, apparatus and system to generate an interrupt by monitoring an external interface In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a ... | 06/10/2008 |
| 7386646 | System and method for interrupt distribution in a multithread processor A system and method for interrupt distribution in a multithread processor are disclosed. A connection between an interrupt and a set of thread processors can be programmed. When the interrupt is executed, the set of thread processors are affected. While executing th... | 06/10/2008 |
| 7386647 | System and method for processing an interrupt in a processor supporting multithread execution A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to the read-only portion of system memory. Upon receipt of an interrupt, ... | 06/10/2008 |
| 7380041 | Managing input/output interruptions in non-dedicated interruption hardware environments Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. Th... | 05/27/2008 |
| 7379418 | Method for ensuring system serialization (quiesce) in a multi-processor environment A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies ... | 05/27/2008 |
| 7380275 | Secure and backward-compatible processor and secure software execution thereon A secure processor assuring application software is executed securely, and assuring only authorized software is executed, monitored modes and secure modes of operation. The former executes application software transparently to that software. The latter verifies exec... | 05/27/2008 |
| 7373504 | Kernel-level cryptographic kernel interface A method for performing a cryptographic function including calling into an encryption framework to perform the cryptographic function, wherein calling into the encryption framework comprises sending a request to perform the cryptographic function from a kernel consu... | 05/13/2008 |
| 7373419 | Method, system, and article of manufacture for increasing network throughput Provided are a method, system, and article of manufacture for managing network throughput. An application identifies at least one network connection of a plurality of network connections, wherein packets arriving via the one network connection require greater resour... | 05/13/2008 |
| 7373446 | Method and system for dynamically patching an operating system's interrupt mechanism In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the hos... | 05/13/2008 |
| 7373448 | Method, system, and program for building a queue to test a device Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from accessing the bus. An initiator transmits I/O requests on the bus to th... | 05/13/2008 |
| 7370193 | Computing system being able to quickly switch between an internal and an external networks and a method thereof The invention discloses a computing system such as a computer, a Personal Digital Assistant, or a mobile phone, being connected both to an internal network and an external network and being able to quickly and safely switch therebetween without being shut down while... | 05/06/2008 |
| 7370082 | Remote invalidation of pre-shared RDMA key Methods, systems, and computer program products for reducing communication overhead to make remote direct memory access more efficient for smaller data transfers. An upper layer protocol or other software creates a receive buffer and a corresponding lookup key for r... | 05/06/2008 |
| 7370217 | Regulating file system device access Device write operations may be controlled by receiving a request to perform a write operation to a device and determining whether the device is activated or inactivated. If the device activated, the device may be accessed to perform the requested write operation. If... | 05/06/2008 |
| 7370130 | Core logic device of computer system A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin... | 05/06/2008 |
| 7366814 | Heterogeneous multiprocessor system and OS configuration method thereof Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt... | 04/29/2008 |
| 7363471 | Apparatus, system, and method of dynamic binary translation supporting a denormal input handling mechanism A method may translate a set of source instructions into a set of target instructions, execute the set of target instructions, and unmask a denormal input control bit if the set of source instructions uses a denormal input handling mechanism. A method may detect at ... | 04/22/2008 |
| 7363412 | Interrupting a microprocessor after a data transmission is complete A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives ... | 04/22/2008 |
| 7363390 | Techniques for managing a storage environment Techniques for managing a storage environment. According to an embodiment of the present invention, high-level application programming interfaces (APIs) are provided that can be used by applications such as storage management applications (e.g., ERM applications, SR... | 04/22/2008 |
| 7363393 | Chipset feature detection and configuration by an I/O device Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware fea... | 04/22/2008 |
| 7363411 | Efficient system management synchronization and memory allocation A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received, a first processor checks the state of a second processor, which may ... | 04/22/2008 |
| 7363407 | Concurrent arbitration of multidimensional requests for interrupt resources The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an in... | 04/22/2008 |
| 7363410 | Flexible interrupt handling methods for optical network apparatuses with multiple multi-protocol optical networking modules An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers to handle interrupts triggered by the function blocks of multi-protocol... | 04/22/2008 |
| 7363409 | Interrupt control system and method for reducing interrupt latency An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one event signal. The control logic provides at least one computer executable ... | 04/22/2008 |
| 7363408 | Interruption control system and method An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a ... | 04/22/2008 |
| 7360213 | Method for promotion and demotion between system calls and fast kernel calls Described is an enhanced application of a fast kernel trap, or kernel function call, in combination with a kernel system call providing a system of handling complications during kernel thread operations. In the event of a complication during kernel function call pro... | 04/15/2008 |
| 7360101 | Apparatus and method for controlling CPU speed transition An apparatus and method for controlling CPU speed transition can use an SMI (System Management Interrupt) signal to perform speed transition of a CPU of a computer such as a notebook computer. However, if the bus master device is in the active state, a control opera... | 04/15/2008 |
| 7359998 | Low-power CD-ROM player with CD-ROM subsystem for portable computer capable of playing audio CDs without supply energy to CPU A low-power audio CD player for portable computers permits operation of the CD-ROM subsystem when power is not being supplied to the computer subsystem. In one embodiment of the invention, the computer subsystem comprises a system CPU, a digital-audio generating cir... | 04/15/2008 |
| 7360060 | Using IMPDEP2 for system commands related to Java accelerator hardware A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determ... | 04/15/2008 |
| 7356721 | Microcomputer and emulation apparatus A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation ... | 04/08/2008 |
| 7356739 | System and program for controlling a distributed processing system The highly reliable distributed system is composed of a communication protocol processing unit which comprises a mailbox for storing a communication message, and executes communication protocol processing between data of an application program and a network controll... | 04/08/2008 |
| 7356630 | Processor control device for stopping processor operation A processor control device includes a processor executing an instruction, a module coupled to the processor through a bus and processing independently from the processor, the module is provided in a plural number and a polling processing unit coupled to each module,... | 04/08/2008 |
| 7356664 | Method and apparatus for transferring data from a memory subsystem to a network adapter for improving the memory subsystem and PCI bus efficiency A method, apparatus, and computer instructions for transferring data from a memory to a network adapter. A request is received to transfer data to a network adapter. An offset is set for a starting address of the data to align the data with an end of a frame in the ... | 04/08/2008 |
| 7353312 | Method and apparatus for detecting conditions for blocking a CPU's receipt of signals returned from a peripheral device A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU, wherein the return signal is a signal transmitted by a system chip in r... | 04/01/2008 |
| 7353342 | Shared lease instruction support for transient blocking synchronization A computer system implementing transient blocking synchronization allows a memory location leased by a first process to be read-accessible to another process. In other words, more than one thread may have read-only type leases on a given memory location at a given t... | 04/01/2008 |
| 7348957 | Real-time dynamic design of liquid crystal display (LCD) panel power management through brightness control According to one embodiment of the present invention, a method of power management for a flat panel display is disclosed. The method includes: receiving image data; determining a segment mode for the received image data; selecting a portion of the received image dat... | 03/25/2008 |
